Industry Expert Blogs

In recent years, many semiconductor companies have successfully shifted chip design from on-premises data centers to the cloud. With monolithic systems on chips (SoCs) and multi-die systems becoming ever-more complex, chip designers increasingly rely on “unlimited” cloud resources and new cloud-native, AI-driven EDA tools to rapidly optimize power, performance, and area (PPA).

Unsurprisingly, cloud-based chip design was the subject of numerous sessions and tracks at the Synopsys Users Group (SNUG) Silicon Valley 2023 conference, including a panel titled “Harnessing the Power of the Cloud: Is the Ecosystem Ready?” During the session, industry experts identified the following four trends driving the rapid migration of EDA tools and chip design workloads to the cloud:

• Ever-increasing compute demands
• Accelerated time-to-market requirements
• Evolving cyber threats and stringent security protocols
• A growing need for more flexible, cost-effective storage options

Read on to learn about key takeaways from the panel experts—and get an in-depth look at how cloud-native EDA tools and pre-optimized hardware platforms are empowering semiconductor companies to accelerate their chip design cycles.

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