Industry Expert Blogs
Can the Semiconductor Industry Overcome Thermal Design Challenges in Multi-Die Systems?Synopsys Blog - Synopsys Editorial Team
May. 23, 2023
With compute demands increasing and Moore’s law waning, integrating multiple dies into a single package to form a multi-die system offers semiconductor companies a more efficient way of meeting aggressive power, performance, area (PPA), and time-to-market requirements. By targeting specific workloads with disaggregated dies, or chiplets, multi-die systems enable designers to scale functionality and rapidly create customized silicon for a wide range of applications including high-performance computing (HPC), automotive, and mobile.
As the broader ecosystem around multi-die systems matures with a full-stack AI-driven EDA suite and industry specifications such as UCIe, semiconductor companies are finding greater opportunities for cost-trade-offs as well as success. Despite these positive developments, designers must still contend with many architectural challenges, including thermal limitations. Indeed, chips packed closely together at high integration densities—typically 10,000 to up to one million I/Os per mm2—generate a considerable amount of heat that doesn’t easily or quickly dissipate.
Search Silicon IP
- Why 2023 Holds Big Promise for Multi-Die Systems
- Intel Embraces the RISC-V Ecosystem: Implications as the Other Shoe Drops
- The design of the NoC is key to the success of large, high-performance compute SoCs
- How Multi-Die Systems Create New Business Opportunities for Semiconductor Companies
- Mitigating Side-Channel Attacks In Post Quantum Cryptography (PQC) With Secure-IC Solutions