Industry Expert Blogs

We wrapped up a great PCI-SIG Developers Conference (DevCon) last week which really showed off the strength and momentum of the PCI Express® community. There was great engagement with everyone who stopped by the booth, and we appreciate the time of everyone who had the chance to do so. While PCIe 5.0 just recently reached the market in the latest state-of-the-art server and client systems, the demand for more bandwidth is unrelenting. So, this DevCon was the opportunity to shine the spotlight on the generation for the next wave of computing systems: PCIe® 6.0.

PCIe 6.0 represents a real watershed event for the standard, because for the first time in its storied history, we’re moving from tried-and-true NRZ to a new signaling scheme, PAM4. With PAM4 signaling (“Pulse Amplitude Modulation with four levels”) you get 2 bits per clock cycle for 4 amplitude levels (00, 01, 10, 11) vs. PCIe 5.0, and earlier generations, which used NRZ modulation with 1 bit per clock cycle and two amplitude levels (0, 1). With PAM4, instead of talking about a clean eye, we need to talk about “three clean eyes” between the four voltage levels.

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