Industry Expert Blogs

If you were building a house, you’d want a solid blueprint outlining a carefully planned layout of where every room, hallway, window, and door should be. Making changes later, while the home is under construction, would be costly and time consuming. Similar considerations apply to chip design, including multi-die systems, where the foundation is built through meticulous architecture planning.

For complex multi-die systems, the stakes are even higher to get the architecture as close to right as possible from the very beginning.

Multi-die systems have emerged in response to the scale and systemic complexities that are threatening the efficacy of Moore’s law. Through heterogeneous integration of dies in a single package, multi-die systems enable accelerated scaling of system functionality, reduced risk and time to market, lower system power, and faster creation of new product variants. They’re becoming the architecture of choice for compute-intensive applications such as high-performance computing, automotive, and mobile.

Moving into the mainstream of the semiconductor world, multi-die systems require a new approach at the architecture planning phase. Even early in the architecture specification process—while drawing the blueprint of the new house—chip designers can’t ignore physical effects such as layout, power, temperature, or even IR-drop. In this blog post, we’ll discuss architecture planning considerations and challenges, and provide insights on methodologies and technologies to achieve multi-die system success. You can also gain additional insights by watching our on-demand, six-part webinar series, “Requirements for Multi-Die System Success.” The series covers multi-die system trends and challenges, early architecture design, co-design and system analysis, die-to-die connectivity, verification, and system health.

Click here to read more ...