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Ever since UCIe™ (Universal Chiplet Interconnect Express™) consortium was formed and version 1.0 of the UCIe specification was released, the chiplet/die-to-die ecosystem has been frenzied. IP architects and developers have their task cut-out for them – to come up with a robust design and implementation that benefits from the heterogenous system without compromising their power, performance, and area (PPA) goals. System architects and designers are busy putting the technology in their next generation SoCs. Verification teams are running against time to create test and coverage plans based on the integrated logic before they receive disintegrated chip RTL.

Let’s review what we have seen in the first revision of the specification.

• Multi-layer protocol: application specific protocol layer, die-to-die adapter and physical layer
• Signalling interface between different layers
  • FDI (flit-aware die-to-die interface) between protocol layer and die-to-die adapter
  • RDI (raw die-to-die interface) between die-to-die adapter and physical layer
  • Physical link interface between two dies
• Separate mainband and sideband interface at all the layers
• Native specifications support for CXL, PCIe and streaming protocol
• Single and multi-module in physical layer interface

While the first revision focused on features for signaling and chiplet architecture, version 1.1 addresses compliance and interoperability to support multi-vendor heterogenous systems.

Let’s demystify what’s happening in newly released specification.

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