Industry Expert Blogs

Of all the steps in the chip development process, verification may be one of the most time-consuming and labor-intensive. As chips grow in size and complexity, there’s an almost endless number of design state spaces that must be evaluated. The goal, of course, is to ensure that the end design will work as intended and to avoid costly respins. The faster that coverage closure can happen, the faster you can get to market.

Manual analysis of design state spaces can only get you so far in terms of actionable insights. If you can get to 100% verification coverage, then you can be assured you’ve found all the design bugs. But how do you know exactly what to write in the coverage definition for your testbench? Did you establish the right coverage goals? And how can you be sure which tests contribute the most to the coverage? So, the cycle ends up involving a lot of repetition: find the bugs, fix the bugs, repeat the cycle until you’ve achieved full coverage and can finally sign off on the RTL.

As Qualcomm highlighted at this spring’s DVCon US 2023 conference, the process gets even trickier for graphic processing unit (GPU) architectures due to their high levels of parallelism. The chipmaker’s engineers found that they were engaging in a substantial manual effort to write semi-directed test cases to hit corner cases at the block and cluster levels.

Fortunately, automation and intelligence are converging to accelerate verification coverage closure. Read on to learn how Qualcomm sped up its time to market using AI-driven chip verification.

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