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In the world of advanced technology and exploration, some missions take us where ordinary microprocessors cannot dare to go. Whether exploring the depths of space or operating in avionics, the presence of intense radiation poses a grave threat to electronic components. To overcome this challenge, engineers have devised a solution: radiation-hardening. Radiation-hardened – or rad-hard – devices are designed to endure harsh radiation-rich environments, ensuring reliability and performance in mission-critical scenarios. In this article, we will uncover some techniques behind the creation of these cutting-edge microprocessors, which can be identified in three stages: radiation hardening, fault tolerance, and radiation testing.

Radiation Hardening Techniques

The general goal of radiation hardening is to ensure a device can maintain proper operation in the presence of ionizing radiation, which can cause transient and permanent faults in electronic components. Some key technology techniques that are used at the process level to design radiation-hardened electronic systems include:

• Tightly Controlled Doping: Careful doping of the silicon is necessary to create transistors that are less sensitive to radiation-induced charge effects. The doping process is optimized to minimize the chances of free charge carriers being trapped and causing faults.
• Silicon-on-Insulator (SOI): SOI technology is used in commercial semiconductor manufacturing and involves placing a layer of insulating material (e.g., silicon dioxide) between the silicon substrate and the active layer. This approach reduces the susceptibility of transistors to latch-up and single-event effects caused by radiation-induced charge build-up.

Examples of techniques applied at the layout and circuit level are:

• Radiation Hardening By Design (RHBD): RHBD involves designing the system with specific layout and circuitry techniques that minimize the impact of radiation-induced faults. This includes hardened latches, interlocks, and redundant elements.

• Guard Rings: Guard rings are structures placed around sensitive nodes in the flip-flop to mitigate the effects of radiation-induced charge deposition. These rings help to redirect and dissipate the charge, reducing the likelihood of Single Event Latchups(SELs).
• Bit Interleaved Memories: This concept revolves around distributing a data word across multiple memory modules in a way that allows simultaneous access to multiple bits of data at once. This prevents a single radiation hit from causing multiple errors on the same data word, which would require stronger error correction codes (ECC) that are more complex and expensive to implement.
• Error Correction Codes (ECCs): ECCs involve adding redundant bits to data to detect and correct errors that may occur due to radiation.

A common technique for adding fault tolerance is to apply Triple Modular Redundancy (TMR): TMR is a technique where three identical units run in parallel, and a voting mechanism is used to determine the correct output. If one unit experiences an error due to radiation, the other two can outvote it and produce the correct result. TMR can be applied to fundamental elements such as registers in a design and at higher levels up to complete computers. One difference here is that triplication at register level can, by voting, typically remove the error after a single clock cycle, while triplication at a higher level in the system requires a unit to be restarted and has a longer recovery time during which the system would be susceptible to additional errors.

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