Industry Expert Blogs

In this fast-paced digital age where speed, performance, and time-to-market are king, chip designers are under pressure to deliver high-performance computing that doesn’t compromise power efficiency. The constant demand for instantaneous data processing and sharing is pushing the boundaries of innovation in chip design. With this context, we revisit and revamp the insights from the Synopsys User Group (SNUG) Silicon Valley event to explore how AI-driven Electronic Design Automation (EDA) is revolutionizing chip design and migration processes, making them more efficient and cost-effective.

We’ve already shared how AI has enabled digital designs to be retargeted to more advanced process nodes, helping to limit or remove the need for redesign. But what about migrating existing designs that are still viable to newer processors that have greater power capabilities? Can the same AI technology be applied to this challenge? Synaptics did just that.

Synaptics is a developer of DisplayLink technology that makes it simple to connect any display to any computer that supports USB or Wi-Fi and provides universal solutions for a range of corporate, home, and embedded applications where easy connectivity of displays enhances productivity. The company’s latest DisplayLink DL-7400 is a universal display dock-on-a-chip that supports ultra-high resolution and refresh rates of up to 4K @ 144 Hz with four simultaneous display outputs from a single PC. It boasts 2x 8K, 4x 4K, 5K/6K on any USB even older GPUs, one dock for all IT needs, 2.5G Ethernet with IoT engine, and signed encrypted firmware.

To achieve this high-performance computing demand, Synaptics designed DL-7400 to run on the ARC HS58 32-bit processor that is based on the ARCv3 instruction set architecture (ISA) that features up to 12 core coherent cluster with up to 16 HW accelerators; coherent, high bandwidth interconnect (800GB/s); and 150+ DSP instructions. However, previous generations of DL-7400 that required less processing power ran on the ARC HS38 32-bit processor that is based on the ARCv2 ISA that offers single issue, 10-stage pipeline, and dual/quad-core implementations.

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