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983 IP
1
100.0
TSMC FPD-Link / OpenLDI / LVDS forwarded clock SERDES Link
Universal LVDS-based interfaces supporting variety of Tx and Rx configurations....
2
100.0
TSMC GF LVDS Tx/Rx with optional CMOS I/O
Flexible I/O cell for data and clock applications that supports differential (and optionally single-ended) Tx and Rx capabilities with no external com...
3
20.0
LVDS IO handling data rate up to 50Mbps with maximum loading 60pF
KA16UGLVDS01ST001 is a LVDS IO handling data rate up to 50Mbps with a maximum loading of 60pF. The differential voltage swing can be programmable from...
4
16.0
On-chip protection against IEC61000-4-2 events
ESD solutions and Analog Pads * All voltage domains (0.85V to 5.0V) * Additional higher voltage ranges in BCD processes * High ESD levels (scal...
5
15.0
Library of LVDS IOs cells for TSMC 40LP
The nSIO2000_TS40LP_2V5_1V1 library is an IO cells library combining various LVDS and general purpose I/O powered at 2.5V/1.1V or 1.8V/1.1V, designed ...
6
15.0
Library of LVDS IOs cells for TSMC 65LP
The nSIO2000_TS65LP_2V5_1V2 library is an IO cells library combining various LVDS and general purpose I/O powered at 2.5V/1.2V or 1.8V/1.2V, designed ...
7
15.0
MIPI D-PHY CSI-2 TX/LVDS TX Combo (Transmitter) in TowerJazz 65BSB
The MXL-LVDS-0p6G-DPHY-1p2G-CSI-2-TX-TW-065BSB is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Allian...
8
15.0
Four Channel (4CH) LVDS Transmitter (Serializer) in TSMC 40LP
The MXL-LVDS-4CH-TX-T-40LP is a high-performance 4-channel LVDS transmitter implemented using digital CMOS technology. With a maximum transmit clock f...
9
11.0
Configurable I/O
High-speed configurable I/O capable of signaling speeds of up to 3.2 GT/s supporting the following I/O standards...
10
10.0
DDR4 & LPDDR4 COMBO IO for memory controller PHY, 3200Mbps, TSMCN22
The DDR4&LPDDR4 COMBO IO is used to transfer the Command/Address/Clk and Data between the memory controller PHY and the DRAM device. The TX is designe...
11
10.0
DDR5 & DDR4 COMBO IO for memory controller PHY, 4800Mbps, TSMCN12
The DDR5&DDR4 COMBO IO is used to transfer the Command/Address/Clk and Data between the memory controller PHY and the DRAM device. The TX is designed ...
12
10.0
Differential Output Buffer - TSMC 6FF
Analog Bits’ Differential Output Driver macros provide a low noise, high performance differential output clock. The output driver design implements a ...
13
10.0
Differential Output Buffer - TSMC N5
Analog Bits’ Differential Output Driver macros provide a low noise, high performance differential output clock. The output driver design implements a ...
14
10.0
Differential Receiver - TSMC 7FF
Analog Bits Differential Signal Receiver macro is a receiver including on-chip termination, and addresses a large portfolio of applications. The Recei...
15
10.0
Differential Signal Receiver - TSMC 6FF
Analog Bits Differential Signal Receiver macro is a receiver including on-chip termination, and addresses a large portfolio of applications. The Recei...
16
10.0
Differential Signal Receiver - TSMC N5
Analog Bits Differential Signal Receiver macro is a receiver including on-chip termination, and addresses a large portfolio of applications. The Recei...
17
10.0
High speed universal LVDS Transceiver
Silvaco’s Low Voltage Differential Signaling (LVDS) I/O library is a high-frequency interface that uses differential signals for data transmission. Ty...
18
10.0
Glitch Detector - TSMC N5
Analog Bits’ Glitch Detector macro comprehensively addresses typical SOC power supply and other voltage glitch monitoring needs in a fully integrated ...
19
10.0
ONFI 3.0 Compatible I/O Buffer - TSMC 28 CLN28HPM
Analog Bits ONFI 3.0 compatible I/O buffer provides a high-speed physical interface solution to support the increasing bandwidths demanded by today’s ...
20
8.0
IGALVDT08B, TSMC CLN28HPM LVDS TX/RX Combo IO
The IGALVDT08B contain a differential driver (TX) and a re-ceiver (RX) for LVDS interface. It supports the data rate up to 1.5Gbps. There are four mac...
21
8.0
IGALVDV05A, TSMC CLN12FFC 6-Channel LVDS Transmitter PHY
IGALVDV05A is a 6-channel LVDS Transmitter PHY IP, which is used mainly in Flat-panel Display. It enables larger, higher resolution displays and lower...
22
6.0
10-bit dual-port 30MHz ~ 85MHz LVDS Tx;
...
23
6.0
SMART - DSMART - ISO 7816 Based Smart Card Reader
The DSMART is a fast, versatile and cost-competitive core intended for smart card reader applications. It provides a communication interface with a sm...
24
6.0
LVDS 10 bits dual port transmitter
...
25
5.0556
A 180nm Flip-Chip IO library with 1.2-1.8V GPIO, 1.8V & 5V analog/RF, 20-36V ultra-low leakage low-cap HV analog and OTP program cell
This silicon proven Certus 180 IO library is specifically tailored to address gaps in the native foundry IO offerings for this node. It features a 1....
26
5.0556
A 2Gbps LVDS Tranceiver in TSMC 28nm
This 1.8V LVDS transceiver, designed for TSMCs 28nm process, delivers high-speed, low-power differential signaling with superior signal integrity. Eng...
27
5.0556
A 2Gbps SLVS Transceiver in TSMC 28nm
This 1.8V SLVS transceiver is a high-performance, low-power I/O solution optimized for TSMCs 28nm process. Designed with 1.8V thick oxide devices and ...
28
5.0556
A Flip-Chip compatible I/O Library in TSMC 180nm BCD with 1.8V GPIO, 1.8V to 3.3V Analog, with associated ESD cells.
Certus’ silicon-proven I/O library in TSMC 180nm BCD provides a reliable and flexible solution for mixed-signal, power management, and BCD application...
29
5.0556
A Flip-Chip compatible I/O Library in TSMC 180nm BCD with 1.8V to 5V GPIO, 1.8V to 5V analog, with ultra low-cap/low-leakage RF solutions.
This silicon proven flip-chip compatible library in TSMC 180nm BCD features a multi-voltage GPIO, 1.8V to 5V analog I/O, and ultra-low capacitance and...
30
5.0556
A radiation-hardened 130nm Wirebond IO library with 3.3V GPIO, LVDS TX & RX, 3.3V I2C open-drain, analog cell and OTP program cell
Key attributes of the 130nm IO library include an extended operational temperature range (-55°C to 200°C), sleep retention, and a built-in power regul...
31
5.0556
A SoundWire 0.9V/1.2V I/O Library
This SoundWireDigital I/O Library in TSMC 55nmLPoffersanadvanced, low-power interface solution for high-performance audio applications. Supporting 0.9...
32
5.0556
A SoundWire Inline 0.9V/2.5V I/O Library
This SoundWire Digital I/O Library in TSMC 55nm LP is a silicon-proven interface solution for high-performance audio applications. Designed for 0.9V/2...
33
5.0556
A Specialized 20V Analog I/O in Standard Low Voltage CMOS
This silicon-proven TSMC 55nm LP 20V ESD cell is a high-voltage electrostatic discharge (ESD) protection solution specifically engineered for low-powe...
34
5.0556
A TSMC 16nm 2Gbps LVDS/SLVS Combo Transceiver
This combo transceiver is a highly configurable 2Gbps transceiver for LVDS or SLVS interfaces. With features like dynamic interface selection, on-die ...
35
5.0556
A TSMC 28nm 1.8V-3.3V Fail-Safe General-Purpose IO & OSC
This 28nm GPIO is designed for high-speed (>150MHz output, >250MHz input) applications. The IO operates at either 1.8V or 3.3V and can dynamically sw...
36
5.0556
A TSMC 28nm Wirebond IO library with dynamically switchable 1.8V/ 3.3V GPIO, 5V I2C open-drain, 1.8V & 3.3V analog, OTP program cell, and HDMI & LVDS protection macros - featured across a variety of metal stack and pad configuration options
A key attribute of the Certus 28nm IO library is its ability to detect and dynamically adjust to a VDDIO supply of 1.8V or 3.3V during system operatio...
37
5.0556
A TSMC 65nm Wirebond IO library with 1-3.3V GPIO, 3.3V pulse-width modulation cell, I2C & SVID open-drain, 3.3V & 5V analog and OTP program cell
Key attributes of our TSMC 65nm IO library include dual independent IO supply rails (1.0V-3.3V & 3.3V) and power-on-control (POC) to place IOs in a lo...
38
5.0556
A Wirebond and FlipChip compatible <80fF ESD Solutions for Multi-Gigabit SerDes Applications.
This silicon-proven TSMC 28nm Digital I/O Library delivers a low-capacitance, high-reliability interface solution optimized for advanced semiconductor...
39
5.0556
A Wirebond/Flipchip compatible I/O Library with 5V GPIO, 5V ODIO, 5V Analog I/O and 5V Power Supply I/O
This silicon-proven, I/O Library features a 5V General Purpose I/O, 5V Open-Drain I/O, 5V Analog I/O, 5V Power Supply and an area efficient 5V ESD pro...
40
5.0556
1.0-3.3V GPIO With I2C Open Drain And 3.3V & 5V Analog Cells in TSMC 65nm
A TSMC 65nm Wirebond IO library with 1-3.3V GPIO, 3.3V pulse-width modulation cell, I2C & SVID open-drain cells, 3.3V & 5V analog cells, OTP program c...
41
5.0556
1.8V/3.3V Fail-Safe Multi-Voltage GPIO
This silicon-proven TSMC 28nm Digital I/O Library delivers a high-performance, low-power interface solution designed for advanced digital applications...
42
5.0556
1.8V/3.3V flipchip I/O library with 4kV HBM ESD protection, I2C compliant ODIO
This library is a production-quality, silicon-proven I/O library in TSMC 12nm technology. Supports multi-voltage GPIOs, capable of operating at 1.8V o...
43
5.0556
1.8V/3.3V Flipchip I/O Library with 4kV HBM, I2C Compliant ODIO and 5V Hot-Plug Detect
This library is a production-quality, silicon-proven I/O library in TSMC 16nm technology. Supports multi-voltage GPIOs, capable of operating at 1.8V o...
44
5.0556
1.8V/3.3V Switchable GPIO With 3.3V I2C Open Drain & Analog in TSMC 22nm
A key attribute of this library is its ability to detect and dynamically adjust to a VDDIO supply of 1.8V or 3.3V during system operation. The GPIO ce...
45
5.0556
1.8V/3.3V Switchable GPIO With 5V I2C Open Drain & Analog in 16nm
16nm & 12nm Flip-Chip IO library with dynamically switchable 1.8V/3.3V GPIO, 5V I2C / SMBUS open-drain cell, 5V OTP cell, 1.8V & 3.3V analog cells, an...
46
5.0556
HDMI, LVDS, RF and Analog Pads Library in 45nm / 40nm
A 1.0V to 5V Analog IO Library that includes an HDMI, LVDS, and Analog/RF Low Capacitance pad set in 45nm/40nm HPM processes. This library is a col...
47
5.0556
Three-Speed Inline I/O Library with ODIO in TSMC 22nm
This silicon-proven, flip chip library in TSMC 22nm boasts three variants of GPIOs and one ODIO. All GPIO and ODIO cells have NS and EW orientation. A...
48
5.0556
Inline Wirebond 1.8V to 3.3V Multi-Voltage GPIO with 5V Open-Drain I/O
This I/O Libraru is a high-performance I/O solution for TSMC 22nm technology, supporting both digital and analog interfaces. Designed for 1.8V3.3V op...
49
5.0556
Controlled Impedance Multi-Protocol I/O Library featuring three I/O cells
This I/O library is a high-performance GPIO solution designed for the TSMC FFC/FCC+ process. This flipchip compatible library provides a robust and fl...
50
5.0556
Specialized 1.2V to 3.3V Fail-Safe GPIO and 3.3V I2C Open-Drain, SPI in TSMC 110nm
This silicon proven, wirebond and flipchip compatible library is particularly tailored to address gaps in the native foundry IO offerings for this nod...