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2827 IP
651
1.0
SMIC 0.18um High Density Standard Cell Library
...
652
1.0
SMIC 0.18um IO Library
SMIC 0.18um process 1.8v/3.3v Generic IO library...
653
1.0
SMIC 0.18um IO Library
...
654
1.0
SMIC 0.18um Isolation Cell Library,1.8v operating voltage
SMIC 0.18um Isolation Cell Library...
655
1.0
SMIC 0.18um LL 5v IO Library
SMIC 0.18um LL process 1.8v/5v Generic IO library...
656
1.0
SMIC 0.18um LL IO Library
SMIC 0.18um LL process 1.8v/3.3v Generic IO library...
657
1.0
SMIC 0.18um Low Leakage 9 track Standard Cell Library,1.8v operating voltage
SMIC 0.18um Low Leakage 9T High-Density Standard Cell Library...
658
1.0
SMIC 0.18um LVDS Transceiver
The LVDS transceiver IP is a Serializer/Deserializer (SERDES) pair that transparently translates 12–bit parallel bus into serial stream. This single s...
659
1.0
SMIC 0.18um LVDS Transceiver/Receiver
This transmitter provides CMOS signal to LVDS, and the receiver provides LVDS signal to CMOS. The data rate between of them can be up to 700Mhz. The L...
660
1.0
SMIC 0.18um Mini-LVDS Transmitter
The Mini-LVDS transmitter converts up to 48-bit or 36-bit RGB parallel data into 6-pair/3-pair of Mini-LVDS data stream that can support transmission ...
661
1.0
SMIC 0.18um ROM Compiler
...
662
1.0
SMIC 0.18um Single-Port/Dual-Port SRAM, Two-Port Register File and Diffusion ROM Compiler
VeriSilicon SMIC 0.18um Synchronous Memory Compiler optimized for Semiconductor Manufacturing International Corporation (SMIC) 0.18um Logic 1P6M Salic...
663
1.0
SMIC 0.18um Single-Port/Dual-Port SRAM, Two-Port Register File and Diffusion ROM Compiler for Linux
VeriSilicon SMIC 0.18um Synchronous Memory Compiler optimized for Semiconductor Manufacturing International Corporation (SMIC) 0.18um Logic 1P6M Salic...
664
1.0
SMIC 0.18um Single-Port/Two-Port Register File Compiler
...
665
1.0
SMIC 0.18um SSTL2
VeriSilicon SMIC 0.18um 1.8V/3.3V SSTL2 I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporati...
666
1.0
SMIC 0.18um SSTL3
VeriSilicon SMIC 0.18um 1.8V/3.3V SSTL3 I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporati...
667
1.0
SMIC 0.18um SSTL_18 I/O
SSTL_18 (Stub Series Terminated Logic for 1.8v) is an electrical interface commonly used with DDR2....
668
1.0
SMIC 0.18umLL 90% shrunk Single-Port/Dual-Port SRAM, Two-Port Register File and Diffusion ROM Compiler
VeriSilicon SMIC 0.16um Low Leakage Process Synchronous Memory Compiler optimized for Semiconductor Manufacturing International Corporation (SMIC) 0.1...
669
1.0
SMIC 0.18umLL Single-Port/Dual-Port SRAM, Two-Port Register File and Diffusion ROM Compiler
VeriSilicon SMIC 0.18um Low Leakage Process Synchronous Memory Compiler optimized for Semiconductor Manufacturing International Corporation (SMIC) 0.1...
670
1.0
SMIC 0.18umLL Single-Port/Dual-Port SRAM, Two-Port Register File and Diffusion ROM Compiler for Linux
VeriSilicon SMIC 0.18um Low Leakage Process Synchronous Memory Compiler optimized for Semiconductor Manufacturing International Corporation (SMIC) 0.1...
671
1.0
SMIC 0.25um 2.5V/3.3V SSTL2 I/O Cell Library
VeriSilicon SMIC 0.25um 2.5V/3.3V SSTL2 I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporati...
672
1.0
SMIC 0.25um 2.5V/3.3V SSTL3 I/O Cell Library
VeriSilicon SMIC 0.25um 2.5V/3.3V SSTL3 I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporati...
673
1.0
SMIC 0.25um High Density Standard Cell Library
...
674
1.0
SMIC 0.25um ROM Compiler
...
675
1.0
SMIC 0.25um Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Diffusion ROM Compiler
VeriSilicon SMIC 0.25um High-Speed Synchronous Memory Compiler optimized for Semiconductor Manufacturing International Corporation (SMIC) 0.25um Logic...
676
1.0
SMIC 0.25um Single-Port/Two-Port Register File Compiler
...
677
1.0
SMIC 55nm LP Multiple Power Supply IO library
Multiple power supply IO library for SMIC55nm low power 1.2v/2.5v process...
678
1.0
SMIC 55nm sub-LVDS Receiver
The sub-LVDS Receiver IP is designed as an interface to bridge Video Image Sensors and processors. The receiver consists of PHY only....
679
1.0
SMIC 55nm sub-LVDS Receiver
The sub-LVDS Receiver IP is designed as an interface to bridge Video Image Sensors and processors. The receiver consists of PHY only....
680
1.0
SMIC 65nm Low Leakage LVDS Receiver
The LVDS Receiver converts up to 10 pairs of LVDS data streams into 70-bit of CMOS data and then feeds the data to the logic core that can support Sin...
681
1.0
SMIC 90nm 9T Standard Cell Library - HVT, 1.2v operating voltage
SMIC 90nm Low-Leakage 9T Standard Cell Library...
682
1.0
SMIC 90nm 9T Standard Cell Library - RVT, 1.2v operating voltage
SMIC 90nm Low-Leakage 9T Standard Cell Library...
683
1.0
SMIC 90nm Power Management Kit, 1.2v operating voltage
SMIC 90nm Power Management Kit Library...
684
1.0
SMIC 90nmLL Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Via1 ROM Compiler
VeriSilicon SMIC 90nm Low-Leakage Process Synchronous Memory Compiler optimized for Semiconductor Manufacturing International Corporation (SMIC) 90nm ...
685
1.0
SMIC13 High Speed process, 1.2/1.5V High Speed Transceiver Logic IO
VeriSilicon SMIC 0.13um 1.2V/1.5V HSTL I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporatio...
686
1.0
SMIC18 General process, Multi-Voltage IO with high voltage voltence
SMIC18 General process, Multi-Voltage IO, driver current: 2mA~16mA when 3.3v IO supply...
687
1.0
SMIC18 General process, Multi-Voltage IO, driver current: 10mA~80mA
SMIC18 General process, Multi-Voltage IO, driver current: 10mA~80mA...
688
1.0
SMIC18 General process, Multi-Voltage IO, High ESD perfermance
SMIC18 General process, Multi-Voltage IO, High ESD perfermance...
689
1.0
Sony Camera LVDS Interface
The SONY_CAM_IF IP Core provides a simple way to connect the Sony® FCB-EV range of cameras to your FPGA. It serves as a direct replacement for an exte...
690
1.0
Programmable Special IO in SMIC0.13um
AR750S13 is a programmable special IO cell supporting various JEDEG standards, such as LVDS, LVTTL, LVCMOS-33/25/18/15, SSTL_3/2/18. The IP is extreme...
691
1.0
NSI 0.13um RFSOI Process Multiple power supply IO library
NSI 0.13um RFSOI 1.8V/2.5V Multiple power supply IO Library...
692
1.0
GSMC 0.11um CIS process LVDS Transceiver Pad
This transmitter provides CMOS signal to LVDS, and the receiver provides LVDS signal to CMOS. The data rate between them can be up to 650Mhz. The LVDS...
693
1.0
CSMC 0.13um 1.2V<->3.3V Level Shifter Library, 1.2v/3.3v operating voltage
CSMC 0.13um 1.2V3.3V Level Shfiter Library...
694
1.0
CSMC 0.13um 3.3V Standard Cell Library, 3.3v operating voltage
CSMC 0.13um 3.3V Standard Cell Library...
695
1.0
GSMC 0.13um 9 track Standard Cell Library - RVT,1.2v operating voltage
GSMC 0.13um 9 track Standard Cell Library...
696
1.0
CSMC 0.13um 9track HVT Standard Cell Library, 1.2v operating voltage
CSMC 0.13um 9track HVT Std Cell Library...
697
1.0
CSMC 0.13um 9track LVT Standard Cell Library, 1.2v operating voltage
CSMC 0.13um 9track LVT Std Cell Library...
698
1.0
TSMC 0.13um 9track Standard Cell Library, 1.2v operating voltage
TSMC 0.13um 9 track Standard Cell Library...
699
1.0
CSMC 0.13um 9track Standard Cell Library, 1.2v operating voltage
CSMC 0.13um 9 track Standard Cell Library...
700
1.0
GSMC 0.13um IO Library
GSMC 0.13um process 1.2v/3.3v Generic IO library...
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