Design & Reuse
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arrow Embedded Memories (1005)
arrow I/O Library (992)
arrow Standard cell (745)
2786 IP
1751
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C90) w/ Forward Bias. W/ deep Nwell.
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C90) w/ Forward Bias. W/ deep Nwell....
1752
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C90). W/O deep Nwell.
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C90). W/O deep Nwell....
1753
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60) w/ Forward Bias. W/ deep Nwell.
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60) w/ Forward Bias. W/ deep Nwell....
1754
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60). W/O deep Nwell
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60). W/O deep Nwell...
1755
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell...
1756
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90).W/O deep Nwell.
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90).W/O deep Nwell....
1757
0.118
UMC 55nm ULP/LowK process Single-Port SRAM
UMC 55nm ULP/LowK process Single-Port SRAM...
1758
0.118
UMC 55nm ULP/LowK process Single-Port SRAM
UMC 55nm ULP/LowK process Single-Port SRAM...
1759
0.118
UMC 55nm ULP/LowK Process Single-Port SRAM with RED Well Biase Memory compiler
UMC 55nm ULP/LowK Process Single-Port SRAM with RED Well Biase Memory compiler...
1760
0.118
UMC 55nm ULP/LowK Process Single-Port SRAM with well bias & RED Memory Compiler
UMC 55nm ULP/LowK Process Single-Port SRAM with well bias & RED Memory Compiler...
1761
0.118
UMC 55nm ULP/LowK Process Single-Port SRAM with well bias HVT Memory Compiler
UMC 55nm ULP/LowK Process Single-Port SRAM with well bias HVT Memory Compiler...
1762
0.118
UMC 55nm ULP/LowK Process via ROM compiler for well bias
UMC 55nm ULP/LowK Process via ROM compiler for well bias...
1763
0.118
UMC 55nm ULP/LowK Process via1 ROM compiler well bias
UMC 55nm ULP/LowK Process via1 ROM compiler well bias...
1764
0.118
UMC 55nm ULP/LowK Single-Port SRAM with Well Bias uHVT
UMC 55nm ULP/LowK Single-Port SRAM with Well Bias uHVT...
1765
0.118
UMC 55nm ULP/LVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60). W/O deep Nwell
UMC 55nm ULP/LVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60). W/O deep Nwell...
1766
0.118
UMC 55nm ULP/LVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60)
UMC 55nm ULP/LVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60)...
1767
0.118
UMC 55nm ULP/LVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60).W/O deep Nwell.
UMC 55nm ULP/LVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60).W/O deep Nwell....
1768
0.118
UMC 55nm ULP/LVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60)
UMC 55nm ULP/LVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60)...
1769
0.118
UMC 55nm ULP/LVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60)
UMC 55nm ULP/LVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60)...
1770
0.118
UMC 55nm ULP/LVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60)
UMC 55nm ULP/LVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60)...
1771
0.118
UMC 55nm ULP/RVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60). W/O deep Nwell.
UMC 55nm ULP/RVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60). W/O deep Nwell....
1772
0.118
UMC 55nm ULP/RVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60). W/O deep Nwell
UMC 55nm ULP/RVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60). W/O deep Nwell...
1773
0.118
UMC 55nm ULP/RVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60). W/O deep Nwell.
UMC 55nm ULP/RVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60). W/O deep Nwell....
1774
0.118
UMC 55nm ULP/RVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60)
UMC 55nm ULP/RVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60)...
1775
0.118
UMC 55nm ULP/RVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60)
UMC 55nm ULP/RVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60)...
1776
0.118
UMC 55nm ULP/RVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60)
UMC 55nm ULP/RVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60)...
1777
0.118
UMC 55nm ULP/uHVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell.
UMC 55nm ULP/uHVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell....
1778
0.118
UMC 55nm ULP/uHVT Low-K Logic Process Process 6-track Generic Core Cell Library (C90) w/ Forward Bias. W/ deep Nwell.
UMC 55nm ULP/uHVT Low-K Logic Process Process 6-track Generic Core Cell Library (C90) w/ Forward Bias. W/ deep Nwell....
1779
0.118
UMC 55nm ULP/uHVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell.
UMC 55nm ULP/uHVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell....
1780
0.118
UMC 55nm ULP/uHVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell.
UMC 55nm ULP/uHVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell....
1781
0.118
UMC 55nm ULP/uHVT Low-K Logic Process Process 8-track Generic Core Cell Library (C90) w/ Forward Bias
UMC 55nm ULP/uHVT Low-K Logic Process Process 8-track Generic Core Cell Library (C90) w/ Forward Bias...
1782
0.118
UMC 55nm ULP/uHVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell.
UMC 55nm ULP/uHVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell....
1783
0.118
UMC 55nm uLP/uHVT LowK Logic Process Ultra High Density (6T) Generic Core Cell Library
UMC 55nm uLP/uHVT LowK Logic Process Ultra High Density (6T) Generic Core Cell Library...
1784
0.118
UMC 65nm LL Lowk Logic Process 1.8V I2C IO for Sony
UMC 65nm LL Lowk Logic Process 1.8V I2C IO for Sony...
1785
0.118
UMC 65nm LL/RVT 1P10M LowK Logic Process 1.8V/3.3V multi-voltage generic I/O cell library
UMC 65nm LL/RVT 1P10M LowK Logic Process 1.8V/3.3V multi-voltage generic I/O cell library...
1786
0.118
UMC 65nm SP LowK Logic Process synchronous single port register file SRAM memory compiler.
UMC 65nm SP LowK Logic Process synchronous single port register file SRAM memory compiler....
1787
0.118
UMC 65nm SP/RVT Logic Process MPCA cell library
UMC 65nm SP/RVT Logic Process MPCA cell library...
1788
0.118
UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler with redundancy.
UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler with redundancy....
1789
0.118
UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler.
UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler....
1790
0.118
UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler.
UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler....
1791
0.118
UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler.
UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler....
1792
0.118
UMC 80nm HV Process High Density Standard Cell Library
UMC 80nm HV Process High Density Standard Cell Library...
1793
0.118
UMC 80nm HV Process PG Single-Port SRAM Memory Compiler_x005F_x005F_x005F_x005F_x005F_x000D_
UMC 80nm HV Process PG Single-Port SRAM Memory Compiler...
1794
0.118
UMC 80nm HV Process Single-Port SRAM Memory Compiler with redundancy
UMC 80nm HV Process Single-Port SRAM Memory Compiler with redundancy...
1795
0.118
UMC 80nm LL/eHV Process synchronous Via ROM memory compiler
UMC 80nm LL/eHV Process synchronous Via ROM memory compiler...
1796
0.118
UMC 90nm LL-RVT (Low-K) Process with 3.3V device analog esd IO group (with BOAC)
UMC 90nm LL-RVT (Low-K) Process with 3.3V device analog esd IO group (with BOAC)...
1797
0.118
UMC 90nm LL/RVT Low-K Logic Process 2.5VOD3.3V Low Frequency OSC BOAC Pad
UMC 90nm LL/RVT Low-K Logic Process 2.5VOD3.3V Low Frequency OSC BOAC Pad...
1798
0.118
UMC 90nm LL/RVT Low-K Logic Process 2.5VOD3.3V Low Frequency OSC pad
UMC 90nm LL/RVT Low-K Logic Process 2.5VOD3.3V Low Frequency OSC pad...
1799
0.118
UMC 90nm LL/RVT LowK process true 3.3V Analog ESD IO cell Library Using 3.3V GOX52 IO
UMC 90nm LL/RVT LowK process true 3.3V Analog ESD IO cell Library Using 3.3V GOX52 IO...
1800
0.118
UMC 90nm LL/RVT LowK process true 3.3V Analog ESD IO cell Library Using 3.3V GOX52 IO
UMC 90nm LL/RVT LowK process true 3.3V Analog ESD IO cell Library Using 3.3V GOX52 IO...