Design & Reuse
Catalog of SIP Cores
System on Chip design resources
arrow Arithmetic & Mathematic (45)
arrow Embedded Memories (994)
arrow I/O Library (1032)
arrow Standard cell (756)
2827 IP
201
5.0556
AM130: 5V GPIO, ODIO, analog & power-supply I/O library, TSMC 130nm 5V Gen3 BCD
A silicon-proven, wirebond/flip-chip-compatible I/O library in TSMC 130nm 5V Gen3 BCD, with 5V GPIO, ODIO, analog, and power-supply I/O plus an area-e...
202
5.0556
PM22: Ultra-low leakage 1.8V GPIO with I2C ODIO & Analog, TSMC 22nm ULL
An ultra-low-leakage I/O library in TSMC 22nm ULL: the GPIO leaks just ~150pA from VDDIO and ~1nA typical from VDD. It pairs a configurable input/outp...
203
5.0556
MM22: Ultra-low leakage dynamic 1.8/3.3V GPIO Library with I2C ODIO & analog, up to xSPI400, TSMC 22nm ULL
An ultra-low-leakage I/O library in TSMC 22nm ULL with a dynamic 1.8–3.3V GPIO that auto-adapts across the supply range with no manual mode switching....
204
5.0556
SN12: 5V Generic I/O & ESD protection Library (>8kV HBM / 8A), TSMC 12nm
A base set of ESD protection structures for I/O and power supplies in TSMC 12nm FFC/FFC+, targeting up to 8A (>8kV HBM). The cells trigger and protect...
205
5.0556
RP65: Multi-Voltage GPIO with PWM, I2C/SVID open-drain, 3.3V/5V analog & OTP, TSMC 65nm
A silicon-proven, wirebond I/O library in TSMC 65nm with dual independent I/O supply rails (1.0–3.3V and 3.3V) and power-on control (POC) to hold I/Os...
206
5.0556
VR13: Radiation-hardened wirebond I/O library with 3.3V GPIO, LVDS, I2C ODIO, analog & OTP, TSMC 130nm
A silicon-proven, radiation-hardened wirebond I/O library in TSMC 130nm, rated for an extended −50°C to 200°C range with sleep-retention and a built-i...
207
5.0556
RS16: Controlled-impedance multi-protocol I/O Library (HP, HV & RCAL macros), TSMC 16nm
A high-performance, flip-chip I/O library in TSMC 16FFC/FFC+ for high-speed digital and mixed-signal designs, offering single-ended and differential I...
208
5.0556
MS18: 1.2-1.8V GPIO with 1.8V/5V analog/RF, 20-36V HV analog & OTP cell, TSMC 180nm
A silicon-proven Certus I/O library for TSMC 180nm, built to fill gaps in the native foundry I/O offering at this node. It pairs a 1.2–1.8V GPIO (dual...
209
5.0556
RS18: 1.8V GPIO with 1.8V/3.3V analog I/O, TSMC 180nm BCD
Certus' silicon-proven I/O library in TSMC 180nm BCD, built for mixed-signal, power-management, and BCD applications. It combines a 1.8V digital I/O (...
210
5.0556
HS18: 1.8V to 5V GPIO & analog I/O library, TSMC 180nm BCD
A silicon-proven, flip-chip-compatible I/O library in TSMC 180nm BCD. It pairs multi-voltage GPIO and 1.8V–5V analog I/O with ultra-low-capacitance, l...
211
5.0556
IS55: Specialized 20V Analog ESD Cell, TSMC 55nm LP
A silicon-proven 20V ESD protection cell in TSMC 55nm LP, built for high-voltage interfaces in analog, mixed-signal, RF, and power-management ICs. Its...
212
5.0556
NV110/IC110: 1.2V/3.3V fail-safe GPIO with 3.3V I2C ODIO & SPI, TSMC 110nm
A silicon-proven I/O library in TSMC 110nm, available in wirebond (NV110) and flip-chip (IC110) variants, built to fill gaps in the native foundry I/O...
213
5.0556
AV55: Low-Capacitance RF ESD Cell Library, TSMC 55nm LP
A production-quality, silicon-proven ESD library in TSMC 55nm LP — not a full I/O, but a collection of standalone, low-capacitance ESD cells for RF an...
214
5.0
1:2 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
215
5.0
1:2 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
216
5.0
1:3 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
217
5.0
1:3 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
218
5.0
1:3 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
219
5.0
1:4 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
220
5.0
1:4 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
221
5.0
1:6 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
222
5.0
1:6 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
223
5.0
Memory Compiler(12nm,16nm,22nm,28nm,40nm,55nm, 90nm, 115nm, 130nm, 150nm, 180nm)
M31 memory compilers are designed with high industrial standards to which provides the memory solutions for density, power, and performance optimizati...
224
5.0
General Purpose I/O (GPIO)(12nm,16nm,22nm, 28nm, 40nm, 55nm, 90nm, 110nm, 130nm, 150nm,152nm, 180nm)
GPIO is a general-purpose input/output unit that provides basic input/output functionalities. M31 provides silicon-proven GPIO libraries in a variety ...
225
5.0
Inline CUP I/O
The inline CUP I/O library provide 3.3V bi- directional I/O cells with pull -up, pull-down features, Schmitt trigger and a range of drive strengths....
226
5.0
eNOR embedded Flash embedded IP
Zhuhai Chuangfeixin’s Floating-gate eNOR Flash memory macro are silicon characterized and qualified on Huali Microelectronics Corporation 65nm Floati...
227
5.0
Integrated ESD cell designs for General I/O, eMMC I/Os, SDIOs, and ONFI I/O(12nm~180nm)
M31’s I/O Libraries now include integrated ESD cell designs for General I/O, eMMC I/Os, SDIOs, and ONFI I/O. We provide standard JEDEC ESD level and c...
228
5.0
IO Library - GlobalFoundries 22FDX
The general purpose 22FDX® IO Library features a rich set of digital and analog IO cells covering 1.2 V to 1.8 V I/O standards and 0.4 V to 0.8 V core...
229
5.0
Special I/O-eMMC/SDIO (22nm, 28nm, and 40nm)
SD (Secureity Digital) and eMMC (embedded MultiMedia Card) I/Os are non-volatile memory interface technologiesy with high bandwidth capabilities, whic...
230
5.0
Standard Cell Library in TSMC (12nm~180nm)
M31 provides a variety of cell libraries, including Ultra-High Density Standard Cell Library (HDSC), General Purpose Standard Cell library (GPSC), Ult...
231
5.0
OTP IP
Zhuhai Chuangfeixin (CFX) offers two proprietary OTP technologies and respective silicon IPs：One is Anti-fuse, the other is floating gate. CFX OTP ...
232
5.0
OTP One Time Programmable IP HHGrace 55HV
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
233
5.0
OTP One Time Programmable IP HHGrace 55LP
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
234
5.0
OTP One Time Programmable IP HHGrace 90BCD
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
235
5.0
OTP One Time Programmable IP HLMC 55CIS
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
236
5.0
OTP One Time Programmable IP Nexchip 110HV
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
237
5.0
OTP One Time Programmable IP Nexchip 110LP2
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
238
5.0
OTP One Time Programmable IP Nexchip 55HV_6V
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
239
5.0
OTP One Time Programmable IP Samsung 90CIS
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
240
5.0
OTP One Time Programmable IP SIL130HV
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
241
5.0
OTP One Time Programmable IP SIL180
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
242
5.0
OTP One Time Programmable IP Silterra 160HV
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
243
5.0
OTP One Time Programmable IP SMIC 153nm
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
244
5.0
OTP One Time Programmable IP SMIC 28HV
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
245
5.0
OTP One Time Programmable IP SMIC 55HV
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
246
5.0
OTP One Time Programmable IP SMIC130
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
247
5.0
OTP One Time Programmable IP XMC 55LL
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
248
4.0556
A radiation-hardened GlobalFoundries 12nm LP/LP+ 0.8V LVDS Transceiver
Certus Semiconductor’s 2.5Gbps LVDS transceiver in GlobalFoundries LP/LP+ is designed for high-speed, low-power data transmission in radiation-intensi...
249
4.0556
A radiation-hardened GlobalFoundries 12nm LP/LP+ 0.8V SLVS Transceiver
This SLVS I/O Library delivers a robust, high-performance solution for high-speed differential signaling in GlobalFoundries 12nm process technology. D...
250
4.0556
1.8V & 3.3V Radiation Hardened GPIO with Optimized LDO in GlobalFoundries 12 LP/LP+
This radiation-hardened, by design, library features both a 1.8 and 3.3V GPIO with multiple drive strengths of 2mA, 4mA,8mA, and 16mA, along with a fu...