Design & Reuse
arrow Arithmetic & Mathematic (34)
arrow Embedded Memories (1006)
arrow I/O Library (958)
arrow Standard cell (745)
2743 IP
201
5.0
OTP IP
Zhuhai Chuangfeixin (CFX) offers two proprietary OTP technologies and respective silicon IPs：One is Anti-fuse, the other is floating gate. CFX OTP ...
202
5.0
OTP One Time Programmable IP HHGrace 55HV
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
203
5.0
OTP One Time Programmable IP HHGrace 55LP
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
204
5.0
OTP One Time Programmable IP HHGrace 90BCD
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
205
5.0
OTP One Time Programmable IP HLMC 55CIS
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
206
5.0
OTP One Time Programmable IP Nexchip 110HV
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
207
5.0
OTP One Time Programmable IP Nexchip 110LP2
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
208
5.0
OTP One Time Programmable IP Nexchip 55HV_6V
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
209
5.0
OTP One Time Programmable IP Samsung 90CIS
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
210
5.0
OTP One Time Programmable IP SIL130HV
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
211
5.0
OTP One Time Programmable IP SIL180
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
212
5.0
OTP One Time Programmable IP Silterra 160HV
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
213
5.0
OTP One Time Programmable IP SMIC 153nm
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
214
5.0
OTP One Time Programmable IP SMIC 28HV
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
215
5.0
OTP One Time Programmable IP SMIC 55HV
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
216
5.0
OTP One Time Programmable IP SMIC130
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
217
5.0
OTP One Time Programmable IP XMC 55LL
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
218
5.0
Fully-integrated Low Voltage Differential Signaling (LDVS) transceiver
The LVDS Transceiver is a fully integrated Low-Voltage Differential Signaling (LVDS) Analog Front End (AFE) including one flow-through driver and two ...
219
5.0
EverOn Ultra Low Voltage Embedded SRAM TSMC 22ULL
sureCore’s EverOn™ Single Port Synchronous Ultra Low Voltage SRAM IP combines high-density foundry bitcells with sureCore’s low-voltage and low-power ...
220
5.0
EverOn Ultra Low Voltage Embedded SRAM TSMC 28HPC+
sureCore’s EverOn™ Single Port Synchronous Ultra Low Voltage SRAM IP combines high-density foundry bitcells with sureCore’s low-voltage and low-power ...
221
5.0
EverOn Ultra Low Voltage Embedded SRAM TSMC 40ULP
sureCore’s EverOn™ Single Port Synchronous Ultra Low Voltage SRAM IP combines high-density foundry bitcells with sureCore’s low-voltage and low-power ...
222
5.0
EverOn Ultra Low Voltage Embedded SRAM TSMC 40ULP Embedded Flash
sureCore’s EverOn™ Single Port Synchronous Ultra Low Voltage SRAM IP combines high-density foundry bitcells with sureCore’s low-voltage and low-power ...
223
4.0
Cryogenic clock multipler. Reference clock up to 30MHz, Output clock up to 1GHz. Operates down to 4K
Our range of CryoCMOS IP is suitable for operation at the extremely low temperature required for Quantum Computing (QC) applications. This CryoIP ™ fa...
224
4.0
Cryogenic Contact Programmable ROM qualified down to 4K operating temperature
Our range of CryoCMOS IP is suitable for operation at the extremely low temperature required for Quantum Computing (QC) applications. This CryoIP ™ fa...
225
4.0
Cryogenic Dual Port Register File qualified down to 4K operating temperature
Our range of CryoCMOS IP is suitable for operation at the extremely low temperature required for Quantum Computing (QC) applications. This CryoIP ™ fa...
226
4.0
Cryogenic SP SRAM qualified down to 4K operating temperature
Our range of CryoCMOS IP is suitable for operation at the extremely low temperature required for Quantum Computing (QC) applications. This CryoIP ™ fa...
227
3.0
A 180nm Flip-Chip IO library with 1.2-1.8V GPIO, 1.8V & 5V analog/RF, 20-36V ultra-low leakage low-cap HV analog and OTP program cell
This silicon proven Certus 180 IO library is specifically tailored to address gaps in the native foundry IO offerings for this node. It features a 1....
228
3.0
A 2Gbps LVDS Tranceiver in TSMC 28nm
This 1.8V LVDS transceiver, designed for TSMCs 28nm process, delivers high-speed, low-power differential signaling with superior signal integrity. Eng...
229
3.0
A 2Gbps SLVS Transceiver in TSMC 28nm
This 1.8V SLVS transceiver is a high-performance, low-power I/O solution optimized for TSMCs 28nm process. Designed with 1.8V thick oxide devices and ...
230
3.0
A Flip-Chip compatible I/O Library in TSMC 180nm BCD with 1.8V GPIO, 1.8V to 3.3V Analog, with associated ESD cells.
Certus’ silicon-proven I/O library in TSMC 180nm BCD provides a reliable and flexible solution for mixed-signal, power management, and BCD application...
231
3.0
A SoundWire 0.9V/1.2V I/O Library
This SoundWireDigital I/O Library in TSMC 55nmLPoffersanadvanced, low-power interface solution for high-performance audio applications. Supporting 0.9...
232
3.0
A SoundWire Inline 0.9V/2.5V I/O Library
This SoundWire Digital I/O Library in TSMC 55nm LP is a silicon-proven interface solution for high-performance audio applications. Designed for 0.9V/2...
233
3.0
A Specialized 20V Analog I/O in Standard Low Voltage CMOS
This silicon-proven TSMC 55nm LP 20V ESD cell is a high-voltage electrostatic discharge (ESD) protection solution specifically engineered for low-powe...
234
3.0
7 track Extra Low Consumption standard cell library with Dual voltage capability (1.8 V / 1.1 V)
TSMC 180 G, SESAME eLC DV is specifically designed to enable robust dual voltage operation, with characterizations taking into account physical phenom...
235
3.0
9 track standard cell library at TSMC 55 nm
Foundry Sponsored, TSMC 55 uLPeF Sesame 9T a unique architecture based on 9-track cells, optimized for High Density and Low Dynamic Power allowing use...
236
3.0
9 track standard cell library at TSMC 55 nm
Foundry Sponsored, TSMC 55 uLP, Sesame 9T, a unique architecture based on 9-track cells, optimized for High Density and Low Dynamic Power allowing use...
237
3.0
6 track Ultra High Density standard cell library at TSMC 55 nm
Foundry Sponsored, TSMC 55 LeFP, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spi...
238
3.0
A TSMC 16nm 2Gbps LVDS/SLVS Combo Transceiver
This combo transceiver is a highly configurable 2Gbps transceiver for LVDS or SLVS interfaces. With features like dynamic interface selection, on-die ...
239
3.0
A TSMC 65nm Wirebond IO library with 1-3.3V GPIO, 3.3V pulse-width modulation cell, I2C & SVID open-drain, 3.3V & 5V analog and OTP program cell
Key attributes of our TSMC 65nm IO library include dual independent IO supply rails (1.0V-3.3V & 3.3V) and power-on-control (POC) to place IOs in a lo...
240
3.0
A Wirebond and FlipChip compatible <80fF ESD Solutions for Multi-Gigabit SerDes Applications.
This silicon-proven TSMC 28nm Digital I/O Library delivers a low-capacitance, high-reliability interface solution optimized for advanced semiconductor...
241
3.0
1.0-3.3V GPIO With I2C Open Drain And 3.3V & 5V Analog Cells in TSMC 65nm
A TSMC 65nm Wirebond IO library with 1-3.3V GPIO, 3.3V pulse-width modulation cell, I2C & SVID open-drain cells, 3.3V & 5V analog cells, OTP program c...
242
3.0
12 track thick oxide standard cell library at TSMC 40 - low leakage and direct battery connection (operating voltages from 1.1 V to 3.3 V)
SESAME BiV 40 uLP a new thick oxyde based standard cell library for ultra low leakage logic design and/or direct battery connection through the use o...
243
3.0
12 track thick oxide standard cell library at TSMC 40 - low leakage and direct battery connection (operating voltages from 1.1 V to 3.3 V)
SESAME BiV 40 uLPeFlash a new thick oxyde based standard cell library for ultra low leakage logic design and/or direct battery connection through the...
244
3.0
12 track thick oxide standard cell library at TSMC 40 - low leakage and direct battery connection (operating voltages from 1.1 V to 3.3 V)
TSMC 40 LPeF, SESAME BiV, a new thick oxyde based standard cell library for ultra low leakage logic design and/or direct battery connection through th...
245
3.0
12 track thick oxide standard cell library at TSMC 40 - low leakage and direct battery connection (operating voltages from 1.1 V to 3.3 V)
SESAME BiV 40 LP a new thick oxyde based standard cell library for ultra low leakage logic design and/or direct battery connection through the use of...
246
3.0
HDMI, LVDS, RF and Analog Pads Library in 45nm / 40nm
A 1.0V to 5V Analog IO Library that includes an HDMI, LVDS, and Analog/RF Low Capacitance pad set in 45nm/40nm HPM processes. This library is a col...
247
3.0
Metal programmable ROM compiler - Memory optimized for low power - compiler range up to 1024 k
Metal programmable ROM compiler - TSMC 90 nm LP - Non volatile memory optimized for low power - compiler range up to 1024 k...
248
3.0
Metal programmable ROM compiler - Memory optimized for low power and high density - compiler range up to 1024 k
Metal programmable ROM compiler - TSMC 152 nm LP - Non volatile memory optimized for low power and high density - compiler range up to 1024 k...
249
3.0
Metal programmable ROM compiler - Memory optimized for low power and high density - Dual Voltage - compiler range up to 1024 k
Metal programmable ROM compiler - TSMC 152 nm G - Non volatile memory optimized for low power and high density - Dual Voltage - compiler range up to 1...
250
3.0
Metal programmable ROM compiler - Memory optimized for low power and high density - Dual Voltage - compiler range up to 1024 k
Metal programmable ROM compiler - TSMC 180 nm G - Non volatile memory optimized for low power and high density - Dual Voltage - compiler range up to 1...