Design & Reuse
Catalog of SIP Cores
System on Chip design resources
arrow Arithmetic & Mathematic (45)
arrow Embedded Memories (994)
arrow I/O Library (1032)
arrow Standard cell (756)
2827 IP
2501
0.0
9 track thick oxide standard cell library at TSMC 180 - low leakage and direct battery connection (operating voltages from 1.62 V to 3.63 V)
TSMC 180 G, SESAME BIV, a new thick oxyde based standard cell library for ultra low leakage logic design and/or direct battery connection through the ...
2502
0.0
9 track thick oxide standard cell library at TSMC 180 - low leakage and direct battery connection (operating voltages from 1.62 V to 3.63 V)
TSMC 180 RF, SESAME BIV, a new thick oxyde based standard cell library for ultra low leakage logic design and/or direct battery connection through the...
2503
0.0
6 track Ultra High Density standard cell library at TSMC 130 nm
Foundry Sponsored, TSMC 130 BCD, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spi...
2504
0.0
6 track Ultra High Density standard cell library at TSMC 130 nm
TSMC 130 G, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spinner cells (densest a...
2505
0.0
6 track Ultra High Density standard cell library at TSMC 180 nm
TSMC 180 BCD, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spinner cells (densest...
2506
0.0
6 track Ultra High Density standard cell library at TSMC 180 nm
TSMC 180 G, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spinner cells (densest a...
2507
0.0
6 track Ultra High Density standard cell library at TSMC 55 nm
TSMC 55 LP, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spinner cells (densest a...
2508
0.0
6 track Ultra High Density standard cell library at TSMC 90 nm with dual voltage capability
TSMC 90 uLL, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spinner cells (densest ...
2509
0.0
6 track Ultra High Density standard cell library at TSMC 90 nm with dual voltage capability
TSMC 90 LPeF, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spinner cells (densest...
2510
0.0
V-by-One Tx IP, Silicon Proven in SMIC 40LL
V-by-One HS technology targets a high-speed data transmission of video signals based on the internal connection of equipment. V-by-One® HS Standard de...
2511
0.0
3.125 Gbps DDR 1-channel CML transmitter
065TSMC_CML_02 core logic interface includes signal pins (INP1, INP2 and INN1, INN2) for data transmission, control pin EN_TX to configure transmitter...
2512
0.0
3.125 Gbps DDR CML receiver
065TSMC_CML_01 core logic interface includes complementary output signal pins (OUTp, OUTn) for data transmission and enable pin EN_RX. PAD_INP and PAD...
2513
0.0
1.2 Gbps LVDS transmitter/receiver
The interface to the core logic in receiver mode includes the signal pins (out_p and out_n) to receive data and the control pins (en_rx, ten, t_cal ar...
2514
0.0
1.25 Gbps 4-Channel LVDS Deserializer in Samsung 28FDSOI
The MXL-LVDS-RX-4CH is a high performance 4-channel LVDS Receiver implemented using digital CMOS technology. Both the serial and parallel data are org...
2515
0.0
1.2V/1.5V Capable General Purpose IO - TSMC 2nm Plus
1.2V/1.5V Capable General Purpose IO - TSMC 2nm Plus...
2516
0.0
1.2V/1.8V Capable General Purpose IO - TSMC 2nm Plus
1.2V/1.8V Capable General Purpose IO - TSMC 2nm Plus...
2517
0.0
3.3V Wide-Range General Purpose I/O Pad Set
The 3.3V General Purpose I/O library provides bidirectional I/O, isolated analog I/O, and a full complement of power cells along with corner and spac...
2518
0.0
3.3V Wide-Range General Purpose I/O Pad Set
The 3.3V General Purpose I/O library provides bidirectional I/O, isolated analog I/O, and a full complement of I/O power, core power, and analog power...
2519
0.0
3.3V Wide-Range General Purpose Inline I/O Pad Set
The 3.3V General Purpose I/O library provides bidirectional I/O, isolated analog I/O, and a full complement of I/O power, core power, and analog power...
2520
0.0
2.4 Gbps LVDS transmitter
065TSMC_LVDS_07 is LVDS transmitter. The interface to the core logic includes differential signal pins (INP and INN) to transmit data, and control pin...
2521
0.0
7.5 Gbps DDR CML IPs library
040TSMC_CML_01 is a library including: • CML receiver (CML_RX); • CML transmitter (CML_TX). • Reference current/voltage source (CML_RS); • Refe...
2522
0.0
2.5V 5V Tolerant GPIO Inline IO Pad Set
The 3.3V General Purpose I/O (5VT) library provides programmable bidirectional I/O’s that are both 5V tolerant and fault tolerant. The I/O’s are prov...
2523
0.0
2.5V 5V Tolerant GPIO Staggered IO Pad Set
The 3.3V General Purpose I/O (5VT) library provides programmable bidirectional I/O’s that are both 5V tolerant and fault tolerant. The I/O’s are prov...
2524
0.0
2.5V General Purpose Inline IO Pad Set
A full range of power pads is provided to enable the system designer different options for separate core power (VDD and VSS) and separate I/O padring ...
2525
0.0
2.5V General Purpose Staggered IO Pad Set
A full range of power pads is provided to enable the system designer different options for separate core power (VDD and VSS) and separate I/O padring ...
2526
0.0
1.6 Gbps DDR Programmable LVDS Transmitter/Receiver
090TSMC_LVDS_02 consists of transmitter (LVDSOUT), receiver (LVDSIN) and a bias. The LVDS transmitter consists of a current source (nominal 3.5mA) tha...
2527
0.0
3.6Kbit EEPROM IP with configuration 28p8w16bit
GF130_EEPROM_01 is a nonvolatile electrically erasable programmable read-only memory (EEPROM) with volume 3.6Kbit, which is organized as 28 pages of 8...
2528
0.0
1.8V Capable I3C - TSMC 2nm
1.8V Capable I3C - TSMC 2nm...
2529
0.0
1.8V Secondary Oxide LVDS pad - TSMC 7nm 7FF,FF+
Dolphin's interface IP for standard I/O and specialty I/O delivers ultra high performance for DDR1/2/3/4, LPDDR2/3, DDR PHY, LVDS, LVPECL, I2C, PCI, S...
2530
0.0
1.8V to 3.3V GPIO and 3.3V LVDS in Skywater S90-LN
This I/O Library is a robust, mixed-signal I/O platform developed for the SkyWater 90 nm (S90-LN) process, designed to support reliable SoC integratio...
2531
0.0
200 Mbps LVDS IP library
055TSMC_LVDS_03 is a library including: • Transmitter LVDS driver (TX_LVDS); • Receiver LVDS driver (RX_LVDS); • Reference current/voltage genera...
2532
0.0
500Mbps LVDS IP library
180TSMC_LVDS_10 is a library including: • Transmitter LVDS driver (TX_LVDS); • Receiver LVDS driver (RX_LVDS); • Transceiver LVDS driver (R...
2533
0.0
1024-bit EEPROM IP with configuration 32p2w16bit
The block is a nonvolatile electrically erasable programmable read-only memory (EEPROM) with volume 1024 bits (16(bit per word) x 2(word per page) x 3...
2534
0.0
2048bits EEPROM with configuration 16p8w16bit
130GF_EEPROM_05 is a nonvolatile electrically erasable programmable read-only memory (EEPROM) with volume 2048bit, which is organized as 16 pages of 8...
2535
0.0
104x1 Bits OTP (One-Time Programmable) IP, VI- 0.15μm 1.8V/6V BCD G2 EPI Process
The ATO00104X1VI150BIO2N2B is organized as a 104-bit by 1 one-time programmable (OTP). This is a kind of non-volatile memory fabricated in VI- 0.15μ...
2536
0.0
512-bit EEPROM (NTLab)
The block is a nonvolatile electrically erasable programmable read-only memory (EEPROM) with volume 512 bits (16(bit per word) x 2(word per page) x 16...
2537
0.0
512-bit EEPROM with configuration 16p1w32bit
The block is a nonvolatile electrically erasable programmable read-only memory (EEPROM) with volume 512 bits (32(bit per word) x 1(word per page) x 16...
2538
0.0
512bit EEPROM IP with configuration 16p2w16bit
180SMIC_EEPROM_09 is a nonvolatile electrically erasable programmable read-only memory (EEPROM) with volume 512 bits which is organized as 16 pages of...
2539
0.0
512x1 Bits OTP (One-Time Programmable) IP, HHGrac- 95nm 1.5V/5V Embedded SONOS Flash (EF095LP)
The ATO00512X1HH095SON3NA is organized as a 512-bits by 1 one-time programmable in parallel mode. This is a kind of non-volatile memory fabricated in ...
2540
0.0
512x1 Bits OTP (One-Time Programmable) IP, MXI- 0.18μm 1.8V/5V CMOS 18B Process
The ATO00512X1MX180LB52ND is organized as a 512-bit by 1 one-time programmable (OTP). This is a type of non-volatile memory fabricated in MXI- 0.18μ...
2541
0.0
512x1 Bits OTP (One-Time Programmable) IP, MXI- 0.18μm 1.8V/5V CMOS 18B Process,Using 5V devices only
The ATO00512X1MX180LB52ND is organized as a 512-bit by 1 one-time programmable (OTP). This is a kind of non-volatile memory fabricated in MXI- 0.18μm ...
2542
0.0
512x1 Bits OTP (One-Time Programmable) IP, MXI- 0.18μm 1.8V/5V CMOS 18B1(BCD_EPI)
The ATO00512X1MX180B152NA is organized as a 512x1 one-time programmable(OTP). This is a type of non-volatile memory fabricated in MXI- 0.18μm CMOS 18B...
2543
0.0
512x1 Bits OTP (One-Time Programmable) IP, MXI- 0.18μm 1.8V/5V Logic Process
The ATO00512X1MX180LA52NA is organized as a 512-bit by 1 one-time programmable (OTP). This is a type of non-volatile memory fabricated in MXIC 0.18μm...
2544
0.0
512x1 Bits OTP (One-Time Programmable) IP, NJR- 0.05μm UD50SP Process
The AT512X1UD50SP0AA is organized as a 512-bit by 1 one-time programmable (OTP). This is a kind of non-volatile memory fabricated in UD50SP process. ...
2545
0.0
512x1 Bits OTP (One-Time Programmable) IP, S-_h-nix HC130SFN 1.8V/2.8V Process
The ATO00512X1HY180CIS3NA is organized as a 512-bit by 1 one-time programmable (OTP). This is a kind of non-volatile memory fabricated in SK_hynix HC...
2546
0.0
512X1 Bits OTP (One-Time Programmable) IP, TSM- 0.18μm SiGe BiCMOS 1.8V/3.3V Process
The ATO00512X1TS180SGE3NA is organized as a 512-bit by 1 one-time programmable (OTP). This is a type of non-volatile memory fabricated in TSMC 0.18μm...
2547
0.0
512x1 Bits OTP (One-Time Programmable) IP, TSM- 152nm 1.8V/3.3V Mixed Signal
The ATO00512X1TS152GMS3NA is organized as a 512-bits by 1 one-time programmable in parallel mode. This is a kind of non-volatile memory fabricated in...
2548
0.0
512x1 Bits OTP (One-Time Programmable) IP, UM- 0.18μm 1.8V/5V BCD Process
The ATO00512X1UM180B502NA is organized as a 512-bit by 1 one-time programmable (OTP). This is a type of non-volatile memory fabricated in UM- 0.18μm B...
2549
0.0
512x1 Bits OTP (One-Time Programmable) IP, VI- 0.15μm BCD Generation-2 Process
The ATO00512X1VI150B252NB is organized as a 512-bit by 1 one-time programmable (OTP). This is a type of non-volatile memory fabricated in VI- 0.15μm B...
2550
0.0
512x1 Bits OTP (One-Time Programmable) IP, VI- 0.15μm BCD Generation-2 Process
The ATO00512X1VI150B252NA is organized as a 512-bit by 1 one-time programmable (OTP). This is a type of non-volatile memory fabricated in VI- 0.15μm B...