Design & Reuse
Catalog of SIP Cores
System on Chip design resources
arrow Arithmetic & Mathematic (45)
arrow Embedded Memories (994)
arrow I/O Library (1032)
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2827 IP
2801
0.0
LVDS TX PHY & Controller
Innosilicon LVDS implements LVDS TIA/EIA protocol. It specifies a low-voltage point-to-point signal interface, which uses a differential driver connec...
2802
0.0
LVDS TX+ (Transmitter) in UMC 40LP
The MXL-LVDS-SR-TX+ is a high performance 4-channel LVDS transmitter implemented using digital CMOS technology. With a maximum transmit clock frequenc...
2803
0.0
LVDS/ MIPI Combo PHY IP, Silicon Proven in SMIC 40LL
The MIPI-LVDS Combo Tx IP is designed for chips that perform high bandwidth data communication while operating at low power consumption. It can be eas...
2804
0.0
LVDS/FPD Link IP, Silicon Proven in GF 28LPe
A physical layer IP for LVDS transmitter. This IP consists of 20-lane (4 x 4D1C) LVDS drivers and supports up to 1.5Gbps data rate. In LVDS mode, both...
2805
0.0
LVDS/FPD Link IP, Silicon Proven in GF 65/55LPe
A transmitter for LVDS with a physical layer IP. This IP has 20 lanes (4 x 4D1C) of LVDS drivers and can handle 1.5Gbps of data rate. Both serial and ...
2806
0.0
LVDS/TTL PHY & Controller
INNOSILICON™ LVDS/TTL IP implements the LVDS TIA/EIA protocol, providing a low-voltage, high-speed point-to-point signal interface. It supports either...
2807
0.0
NVM EEPROM NeoEE in DBHitek(180nm, 90nm)
eMemory's NeoEE IP is a cost-effective embedded EEPROM solution for both foundries & customers. No additional masks are required, and NeoEE gives foun...
2808
0.0
NVM MTP in DB HiTek (130nm)
Synopsys Non-Volatile Memory (NVM) IP provides reprogrammable NVM supporting up to 1 million bits (1Mbit) configurations in standard CMOS and BCD proc...
2809
0.0
Two port register file (1R1W) with low power retention mode
Low Leakage. Mobile Semiconductor's Bulk 22 ULL Register file memory compiler generates dual port Register File instances using the Bulk 22ULL proces...
2810
0.0
Two Port Register File compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 64 k
Foundry sponsored - Two Port Register File compiler - TSMC 55 nm uLP - Memory optimized for high density and low power - Dual Voltage - compiler range...
2811
0.0
Two Port Register File Compiler IP, UMC 40nm LP process
UMC 40nm LP/ Low-K process, Two Port Register File memory compiler....
2812
0.0
1x32 Bits OTP (One-Time Programmable) IP, TSM- 0.18μm SiGe BiCMOS 1.8V/3.3V Process
The ATO0001X32TS180SGE3NA is organized as 1 by 32 bits one-time programmable (OTP). This is a kind of non-volatile memory fabricated in 0.18um SiGe Bi...
2813
0.0
1x64 Bits OTP (One-Time Programmable) IP, TSM- 0.18μm Mixed-Signal 1.8V/3.3V Process
The AT1X64T180MM0AB is organized as one by 64 bits one-time programmable (OTP). This is a kind of non-volatile memory fabricated in TSM- Mixed-Signal ...
2814
0.0
Synopsys High-Speed Test IO in TSMC N3P
AI and HPC are transitioning to chiplet-based designs to overcome scaling limits of monolithic SoCs and achieve superior performance. While heterogene...
2815
0.0
Synopsys Memory, Logic, IO for DB HiTek 180nm
Synopsys provides designers with high-speed, high-density and low-power memory compilers for the DB HiTek 180nm process technology. The Synopsys Embed...
2816
0.0
Synopsys Memory, Logic, IO for GlobalFounfries 22FDX
Synopsys provides designers with a broad portfolio of high-speed (HS), high-density (HD), high-density low-leakage (HD-LL) and low-power memory compil...
2817
0.0
Synopsys Memory, Logic, IO for GlobalFounfries 22FDX+
Synopsys provides designers with a broad portfolio of Foundation IP that includes high-speed (HS), high-density (HD), and low-power (LP) memory compil...
2818
0.0
Synopsys Memory, Logic, IO for Intel 16
Synopsys provides system-on-chip (SoC) designers with an extensive offering of high-quality foundation IP including high-speed (HS), ultra-high-densit...
2819
0.0
Synopsys Memory, Logic, IO for Intel 18A
Synopsys provides system-on-chip (SoC) designers with an extensive offering of high-quality foundation IP, including memory compilers, logic libraries...
2820
0.0
Synopsys Memory, Logic, IO for Samsung 8LPU
Synopsys provides system-on-chip (SoC) designers with an extensive offering of high-quality foundation IP, including memory compilers, logic libraries...
2821
0.0
Synopsys Memory, Logic, IO for SMIC 40LL
Synopsys provides designers with a broad portfolio of high-speed, high-density and low-power memory compilers and logic libraries. The Synopsys Duet P...
2822
0.0
Synopsys Memory, Logic, IO for SMIC 65LL
Synopsys provides designers with a broad portfolio of high-speed, high-density and low-power memory compilers and logic libraries. The Synopsys Duet P...
2823
0.0
Synopsys Memory, Logic, IO for TSMC 40LP
Synopsys provides designers with a broad portfolio of high-speed, high-density and low-power memory compilers and logic libraries. The Synopys Duet Pa...
2824
0.0
Synopsys Memory, Logic, IO for TSMC 65LP
Synopsys provides designers with a broad portfolio of high-speed, high-density and low-power memory compilers and logic libraries. The Synopsys Duet P...
2825
0.0
Synopsys Memory, Logic, IO for UMC 40ULP
Synopsys provides designers with a broad portfolio of high-speed, high-density and low-power memory compilers and logic libraries. The Synopsys Duet P...
2826
0.0
Synthesizable 3DIO IP for Flexible Physical Implementation
Synopsys 3DIO is a specialized IO for multi-die integration. It includes multiple IP offerings for system-on-chip (SoC) designers to implement tunable...
2827
0.0
VZ55: 1.8V/3.3V GPIO with I2C ODIO, analog I/O, GlobalFoundries 55nm
A production-ready I/O library on GlobalFoundries 55nm CMOS, delivering a full digital and analog I/O suite with 2kV HBM / 500V CDM ESD and latch-up i...