Design & Reuse
Catalog of SIP Cores
System on Chip design resources
arrow Arithmetic & Mathematic (72)
arrow Embedded Memories (996)
arrow I/O Library (1032)
arrow PLL (1747)
arrow Standard cell (756)
4603 IP
3401
0.0
6 track Ultra High Density standard cell library at TSMC 90 nm with dual voltage capability
TSMC 90 uLL, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spinner cells (densest ...
3402
0.0
6 track Ultra High Density standard cell library at TSMC 90 nm with dual voltage capability
TSMC 90 LPeF, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spinner cells (densest...
3403
0.0
9-bit programmable ECL HF divider
The 9-bit programmable ECL high-frequency divider is a set of serially connected dividers with the varied dividing ratio 2/3 which is able to scale th...
3404
0.0
V-by-One Tx IP, Silicon Proven in SMIC 40LL
V-by-One HS technology targets a high-speed data transmission of video signals based on the internal connection of equipment. V-by-One® HS Standard de...
3405
0.0
0.1 to 1 GHZ Frequency Divider
...
3406
0.0
3.125 Gbps DDR 1-channel CML transmitter
065TSMC_CML_02 core logic interface includes signal pins (INP1, INP2 and INN1, INN2) for data transmission, control pin EN_TX to configure transmitter...
3407
0.0
3.125 Gbps DDR CML receiver
065TSMC_CML_01 core logic interface includes complementary output signal pins (OUTp, OUTn) for data transmission and enable pin EN_RX. PAD_INP and PAD...
3408
0.0
1.13GHz to 1.127GHz Integer-N LC Phase-Locked Loop
Frequency synthesizer built on PLL by dividing the integer coefficients. Synthesizer unit includes: R-divider of external reference oscillator frequen...
3409
0.0
1.2 Gbps LVDS transmitter/receiver
The interface to the core logic in receiver mode includes the signal pins (out_p and out_n) to receive data and the control pins (en_rx, ten, t_cal ar...
3410
0.0
1.25 Gbps 4-Channel LVDS Deserializer in Samsung 28FDSOI
The MXL-LVDS-RX-4CH is a high performance 4-channel LVDS Receiver implemented using digital CMOS technology. Both the serial and parallel data are org...
3411
0.0
2.26GHz/2.46GHz Fractional-N LC Phase-Locked Loop with oscillator
180XFAB_PLL_01 uses 2.25792GHz/2.4576GHz Phase locked loop frequency synthesizer for clock generation. It consists of the following main sub-blocks: r...
3412
0.0
1.2V/1.5V Capable General Purpose IO - TSMC 2nm Plus
1.2V/1.5V Capable General Purpose IO - TSMC 2nm Plus...
3413
0.0
1.2V/1.8V Capable General Purpose IO - TSMC 2nm Plus
1.2V/1.8V Capable General Purpose IO - TSMC 2nm Plus...
3414
0.0
3.3V Wide-Range General Purpose I/O Pad Set
The 3.3V General Purpose I/O library provides bidirectional I/O, isolated analog I/O, and a full complement of power cells along with corner and spac...
3415
0.0
3.3V Wide-Range General Purpose I/O Pad Set
The 3.3V General Purpose I/O library provides bidirectional I/O, isolated analog I/O, and a full complement of I/O power, core power, and analog power...
3416
0.0
3.3V Wide-Range General Purpose Inline I/O Pad Set
The 3.3V General Purpose I/O library provides bidirectional I/O, isolated analog I/O, and a full complement of I/O power, core power, and analog power...
3417
0.0
2.4 Gbps LVDS transmitter
065TSMC_LVDS_07 is LVDS transmitter. The interface to the core logic includes differential signal pins (INP and INN) to transmit data, and control pin...
3418
0.0
1.4GHz Frac-N PLL
This is an analog PLL frequency synthesizer, which can generate independent clock with frequency range from 25MHz to 1.4GHz. It supports 4MHz to 180MH...
3419
0.0
2.4GHz ISM Band ADPLL
The Orca Systems™ ORC9010 is a synthesized or synthesizable low-power all-digital phase-locked loop (ADPLL) Digital IP designed for 2.4GHz ISM band Io...
3420
0.0
7.5 Gbps DDR CML IPs library
040TSMC_CML_01 is a library including: • CML receiver (CML_RX); • CML transmitter (CML_TX). • Reference current/voltage source (CML_RS); • Refe...
3421
0.0
4.5GHz Fractional PLL in SMIC 28HKC+
High performance Fractional-N PLL IP supports 24-bit fractional accuracy, a maximum output frequency of 4.5GHz and Spread Spectrum Clocking (SSC) func...
3422
0.0
4.5GHz Fractional PLL in SMIC 28HKD 1.8V
High performance Fractional-N PLL IP supports 24-bit fractional accuracy, a maximum output frequency of 4.5GHz and Spread Spectrum Clocking (SSC) func...
3423
0.0
4.5GHz Fractional PLL in SMIC 28HKD 2.5V
High performance Fractional-N PLL IP supports 24-bit fractional accuracy, a maximum output frequency of 4.5GHz and Spread Spectrum Clocking (SSC) func...
3424
0.0
8.5GHz Fractional-N/SSC PLL
The ll_pllf0435s02_ln04lpp_3207002 is a 1.2V/0.75V dual supply-voltage phase locked loop (PLL) with a wide-output-frequency-range for frequency synthe...
3425
0.0
8.5GHz Fractional-N/SSC PLL
PLLF0435S04 is a 1.2V/0.75V dual supply-voltage phase locked loop (PLL) with a wide-output-frequency-range for frequency synthesis. It consists of a ...
3426
0.0
3.5GHz to 7GHz Low Noise Fractional-N LC Phase-Locked Loop
055TSMC_PLL_02 is a PLL frequency synthesizer that generates a high-frequency signal in the range from 3.5GHz to 7GHz. The synthesizer consists of 4 v...
3427
0.0
2.5V 5V Tolerant GPIO Inline IO Pad Set
The 3.3V General Purpose I/O (5VT) library provides programmable bidirectional I/O’s that are both 5V tolerant and fault tolerant. The I/O’s are prov...
3428
0.0
2.5V 5V Tolerant GPIO Staggered IO Pad Set
The 3.3V General Purpose I/O (5VT) library provides programmable bidirectional I/O’s that are both 5V tolerant and fault tolerant. The I/O’s are prov...
3429
0.0
2.5V General Purpose Inline IO Pad Set
A full range of power pads is provided to enable the system designer different options for separate core power (VDD and VSS) and separate I/O padring ...
3430
0.0
2.5V General Purpose Staggered IO Pad Set
A full range of power pads is provided to enable the system designer different options for separate core power (VDD and VSS) and separate I/O padring ...
3431
0.0
1.6 Gbps DDR Programmable LVDS Transmitter/Receiver
090TSMC_LVDS_02 consists of transmitter (LVDSOUT), receiver (LVDSIN) and a bias. The LVDS transmitter consists of a current source (nominal 3.5mA) tha...
3432
0.0
1.68GHz to 1.917GHz Integer-N LC Phase-Locked Loop
Frequency synthesizer built on PLL by dividing the integer coefficients. Synthesizer unit includes: R-divider of external reference oscillator frequen...
3433
0.0
3.6Kbit EEPROM IP with configuration 28p8w16bit
GF130_EEPROM_01 is a nonvolatile electrically erasable programmable read-only memory (EEPROM) with volume 3.6Kbit, which is organized as 28 pages of 8...
3434
0.0
5.8GHz Fractional-N LC Phase-Locked Loop
130GF_PLL_02 is intended for SoC clock generation with support of BFSK modulation up to 4Mbps output data rate. PLL IP block embeds a reference 8MHz/1...
3435
0.0
2.8GHz to 3.3GHz Fractional-N LC Phase-Locked Loop
PLL is an automatic control system adjusting controlled oscillator frequency to be equal to reference oscillator frequency multiplied by a given integ...
3436
0.0
2.8GHz to 3.3GHz Fractional-N LC Phase-Locked Loop
PLL is an automatic control system adjusting controlled oscillator frequency to be equal to reference oscillator frequency multiplied by a given integ...
3437
0.0
1.8V Capable I3C - TSMC 2nm
1.8V Capable I3C - TSMC 2nm...
3438
0.0
1.8V Secondary Oxide LVDS pad - TSMC 7nm 7FF,FF+
Dolphin's interface IP for standard I/O and specialty I/O delivers ultra high performance for DDR1/2/3/4, LPDDR2/3, DDR PHY, LVDS, LVPECL, I2C, PCI, S...
3439
0.0
2/64/128 CMOS/ECL PLL high-frequency divider
The CMOS high-frequency divider consists of two independent circuits. The first divider is a set of serially connected CMOS dividers with a dividing r...
3440
0.0
200 Mbps LVDS IP library
055TSMC_LVDS_03 is a library including: • Transmitter LVDS driver (TX_LVDS); • Receiver LVDS driver (RX_LVDS); • Reference current/voltage genera...
3441
0.0
200 MHz—800 Mhz Phase Locked Loop (PLL) IP Block X-FAB 180nm
The PLL200MT800M is a ultra-low power phase locked loop (PLL) intellectual property (IP) block. It features a very small area footprint, with exc...
3442
0.0
2000 to 2800 MHz Phase Locked Loop
...
3443
0.0
500Mbps LVDS IP library
180TSMC_LVDS_10 is a library including: • Transmitter LVDS driver (TX_LVDS); • Receiver LVDS driver (RX_LVDS); • Transceiver LVDS driver (R...
3444
0.0
400MHz Integer-N Low power PLL
This is an analog Integer-N PLL frequency synthesizer, which can generate independent clock with frequency range from 6.25MHz to 800MHz.It supports 4M...
3445
0.0
100MHz to 1200MHz Fractional-N LC Phase-Locked Loop
055TSMC_PLL_08 is a frequency synthesizer with a fractional division ratio and a quadrature output of the heterodyne signal intended for formation, st...
3446
0.0
1024-bit EEPROM IP with configuration 32p2w16bit
The block is a nonvolatile electrically erasable programmable read-only memory (EEPROM) with volume 1024 bits (16(bit per word) x 2(word per page) x 3...
3447
0.0
2048bits EEPROM with configuration 16p8w16bit
130GF_EEPROM_05 is a nonvolatile electrically erasable programmable read-only memory (EEPROM) with volume 2048bit, which is organized as 16 pages of 8...
3448
0.0
104x1 Bits OTP (One-Time Programmable) IP, VI- 0.15μm 1.8V/6V BCD G2 EPI Process
The ATO00104X1VI150BIO2N2B is organized as a 104-bit by 1 one-time programmable (OTP). This is a kind of non-volatile memory fabricated in VI- 0.15μ...
3449
0.0
10MHz to 50MHz Fractional-N LC Phase-Locked Loop
APLL Fractional-N phase locked loop frequency synthesizer is intended for SoC clock generation and embeds a reference 10MHz – 50MHz XTAL oscillator, w...
3450
0.0
512-bit EEPROM (NTLab)
The block is a nonvolatile electrically erasable programmable read-only memory (EEPROM) with volume 512 bits (16(bit per word) x 2(word per page) x 16...