Design & Reuse
Catalog of SIP Cores
System on Chip design resources
arrow Arithmetic & Mathematic (46)
arrow Embedded Memories (994)
arrow I/O Library (1032)
arrow Standard cell (756)
2828 IP
401
1.0
16K32 MTP
XRS011LGCMTP_16K32 is a logic compatible embedded non-volatile memory IP with 16K32 ROM density. This IP could be used for code storage, firmware upd...
402
1.0
16K8 MTP
XRF018BCDLFLASH_16K8 is a BCD compatible embedded non-volatile memory IP with 16K8 ROM density. This IP could be used for code storage, firmware upda...
403
1.0
16K8 MTP
XRX018BCDMTP_16K8B is a BCD compatible embedded non-volatile memory IP with 16k8 ROM density. This IP could be used for code storage, firmware update...
404
1.0
16K8 MTP
XRX018BCDMTP_16K8A is a BCD compatible embedded non-volatile memory IP with 16k8 ROM density. This IP could be used for code storage, firmware update...
405
1.0
16X8 MTP
XRS018BCDMTP_16X8 is a BCD compatible embedded non-volatile memory IP with 16X8 ROM density. This IP could be used for code storage, firmware update,...
406
1.0
UA11: 200Mbps 1.2V SLVS transceiver, UMC 110nm
A compact 1.2V SLVS transceiver in UMC 110nm for high-speed, low-power links. It provides JESD8-13-compliant TX and RX paths up to 200Mbps with strong...
407
1.0
TA18: 1.5V - 3.3V GPIO Library with tri-state driver & 7V OTP, GlobalFoundries 180nm BCD Lite
A silicon-proven wirebond GPIO library in GlobalFoundries 180nm BCD Lite — a specialty I/O in the SoundWire family — with a 1.5V–3.3V multi-voltage GP...
408
1.0
JA65: High-speed 3.3V GPIO/LVDS TX/ODIO Library with 8kV ESD & RF Cell, TPSCo 65nm
A silicon-proven I/O library for TPSCo 65nm CMOS with 1.2V core / 3.3V I/O on a 1P7M1L1F stack with aluminum RDL. It includes GPIO, 5V-tolerant I2C-co...
409
1.0
PAD - SMIC 110nm generic
...
410
1.0
Samsung 28nm FDSOI 1.8v/1.0v LVDS Transmitter
...
411
1.0
Samsung 28nm FDSOI 1.8v/1.0v sub-LVDS Receiver
...
412
1.0
Samsung 28nm Low Power Single-Port SRAM Compiler
VeriSilicon Samsung 28FDSOI Low Power Synchronous Single-Port SRAM compiler optimized for Samsung FDSOI 28nm process can flexibly generate memory bloc...
413
1.0
Samsung 28nm Low Voltage Single-Port SRAM Compiler
VeriSilicon Samsung 28FDSOI Low Voltage Synchronous Single-Port SRAM compiler optimized for Samsung FDSOI 28nm process can flexibly generate memory bl...
414
1.0
IBM 65nm LPE 1.2V<->3.3V Level Shifter
IBM 65nm LPE 1.2V3.3V Level Shifter Library...
415
1.0
IBM 65nm LPE 1.2V<->3.3V Level Shifter
IBM 65nm LPE 1.2V3.3V Level Shifter Library...
416
1.0
IBM 65nm LPE 3.3V Standard Cell
IBM 65nm LPE 3.3V Standard Cell Library...
417
1.0
IBM 65nm LVDS Receiver
The LVDS Receiver converts up to 10 pairs of LVDS data streams into 70-bit of CMOS data and then feeds the data to the logic core that can support Sin...
418
1.0
IBM 65nm LVDS Transmitter
The LVDS transmitter is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolution and Dual Link tra...
419
1.0
IBM 65nm LVDS Transmitter
The LVDS transmitter converts 28-bit data into 4-pair LVDS data stream. A phase-locked transmit clock is transmitted in parallel with the data stream ...
420
1.0
IBM 65nm Mini-LVDS Transmitter
The Mini-LVDS transmitter converts up to 64-bit CMOS data into 16-pairs of Mini-LVDS data stream that can support Single-Link transmission with up to ...
421
1.0
ICRD 0.5um IO library
ICRD 0.5um process 5V Generic IO library...
422
1.0
MCU PAD - SMIC 55nm Eflash
...
423
1.0
MCU PAD - SMIC 55nm Eflash
...
424
1.0
MCU PAD - SMIC 55nm Eflash
...
425
1.0
WD28 / SC28: sub 80fF ESD Macro for multi-gigabit SerDes, TSMC 28nm
A silicon-proven, ultra-low-capacitance ESD macro in TSMC 28nm for multi-gigabit SerDes, available in wirebond (WD28) and flip-chip (SC28) variants. I...
426
1.0
HDMI, LVDS, RF and Analog Pads Library in 45nm / 40nm in TSMC 45/40nm
A 1.0V to 5V Analog IO Library that includes an HDMI, LVDS, and Analog/RF Low Capacitance pad set in 45nm/40nm HPM processes. This library is a col...
427
1.0
TE55: 0.9V/2.5V SoundWire audio I/O Library, TSMC 55nm LP
A silicon-proven 0.9V/2.5V in-line I/O library in TSMC 55nm LP, purpose-built as a SoundWire interface for high-performance, low-power audio. It provi...
428
1.0
SEC 10nm Multi-Bit Standard Cell Library, 0.45V operation voltage
SEC 10nm 4Multi-Bit Flip-Flop Std Cell Library...
429
1.0
SEC 14nm Multi-Bit Standard Cell Library, 0.5V operation voltage
SEC 14nm 4Multi-Bit Flip-Flop Std Cell Library...
430
1.0
SEC 5nm LVH 6T Multi-Bits Latch
SEC 5nm LVH 6 track High Density Multi-Bits Latch...
431
1.0
VeriSilicon CHRT 0.13um 1.2V/2.5V DUPIO_01 Library
VeriSilicon CHRT 0.13um 1.2V/2.5V DUP I/O Cell Library developed by VeriSilicon is optimized for Chartered Semiconductor Manufacturing (CHRT) 0.13um L...
432
1.0
VeriSilicon CHRT 0.13um 1.2V/3.3V DUPIO_01 Library
VeriSilicon CHRT 0.13um 1.2V/3.3V DUP I/O Cell Library developed by VeriSilicon is optimized for Chartered Semiconductor Manufacturing (CHRT) 0.13um L...
433
1.0
VeriSilicon GSMC 0.18um 1.8v/3v/5v Mult IO for SIMcard
VeriSilicon GSMC 0.18um 1.8V/3.3V Multiple I/O Cell (08) Library developed by VeriSilicon is optimized for Grace Semiconductor Manufacturing Corporati...
434
1.0
VeriSilicon GSMC 0.18um (LP) 1.8V/3.3V Multiple I/O
VeriSilicon GSMC 0.18um (LP) 1.8V/3.3V Multiple I/O Cell (01E) Library developed by VeriSilicon is optimized for Grace Semiconductor Manufacturing Cor...
435
1.0
VeriSilicon GSMC 0.18um 1.8V/3.3V Multiple DUP I/O
VeriSilicon GSMC 0.18μm 1.8V/3.3V Multiple DUP I/O Cell (01E) Library developed by VeriSilicon is optimized for Grace Semiconductor Manufacturing Corp...
436
1.0
VeriSilicon GSMC 0.18um 1.8V/3.3V Multiple I/O (05) Library
VeriSilicon GSMC 0.18um 1.8V/3.3V Multiple I/O Cell (05) Library developed by VeriSilicon is optimized for Grace Semiconductor Manufacturing Corporati...
437
1.0
VeriSilicon GSMC 0.18um General Process, Low Power circuit design, Diffusion ROM
VeriSilicon GSMC 0.18um Synchronous Low Power Diffusion ROM compiler optimized for Grace Semiconductor Manufacturing Corporation (GSMC) 0.18um Logic/A...
438
1.0
VeriSilicon GSMC 0.18um Synchronous Low Power Via1 ROM Compiler, Memory Array Range:128 to 2Mega Bits
VeriSilicon GSMC 0.18um Synchronous Programmable Low Power Via1 ROM compiler optimized for Grace Semiconductor Manufacturing Corporation (GSMC) 0.18um...
439
1.0
VeriSilicon IBM 65nm 1.0V/2.5V VPPIO_01 IO Library
VeriSilicon IBM 65nm 1.0V/2.5V VPPIO_01 IO library developed by VeriSilicon is optimized for IBM 65nm 10sf 1.0/2.5V process. This library provides 6.5...
440
1.0
VeriSilicon SMIC 0.11um 1.2V/3.3V ANALOGIO_DUP_05 IO Library
VeriSilicon SMIC 0.11um 1.2V/3.3V ANALOGIO_DUP_05 IO library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corpo...
441
1.0
VeriSilicon SMIC 0.11μm 1.2V/3.3V DUPIO_01 Library
VeriSilicon SMIC 0.11μm 1.2V/3.3V DUP I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporation...
442
1.0
VeriSilicon SMIC 0.13um 1.2V/2.5V ANALOGIO_DUP_05 IO Library
VeriSilicon SMIC 0.13um 1.2V/2.5V ANALOGIO_DUP_05 IO library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corpo...
443
1.0
VeriSilicon SMIC 0.13um 1.2V/3.3V Multiple DUP I/O Cell
VeriSilicon SMIC 0.13um 1.2V/3.3V Multiple DUP I/O Cell (05) Library developed by VeriSilicon supports power/ground pads, bi-directional I/O, IU (bi-d...
444
1.0
VeriSilicon SMIC 0.13um 1.2V/3.3V Multiple I/O 01C Library
VeriSilicon SMIC 0.13μm 3.3V Multiple I/O 01C Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corpora...
445
1.0
VeriSilicon SMIC 0.13um 1.2V/3.3V Multiple I/O Cell
VeriSilicon SMIC 0.13um 1.2V/3.3V Multiple I/O Cell (05) Library developed by VeriSilicon supports power/ground pads, bi-directional I/O, bidirectiona...
446
1.0
VeriSilicon SMIC 0.13um 1.2V/3.3V Multiple I/O Cell
VeriSilicon SMIC 0.13um 1.2V/3.3V Multiple I/O Cell (06) Library developed by VeriSilicon supports power/ground pads, bi-directional I/O, and input bu...
447
1.0
VeriSilicon SMIC 0.13um 1.2V/3.3V SSTLCOMBO_01 I/O Cell Library
VeriSilicon SMIC 0.13μm SSTL2/SSTL3 Combo I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corpora...
448
1.0
VeriSilicon SMIC 0.13um 1.2V/3.3V SSTLCOMBO_02 I/O Cell Library
VeriSilicon SMIC 0.13μm SSTL2/SSTL18 Combo I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corpo...
449
1.0
VeriSilicon SMIC 0.13um High-Speed Synchronous Single-Port SRAM compiler, Memory Array Range:256 to 128K Bits
VeriSilicon SMIC 0.13um High-Speed Synchronous Single-Port SRAM compiler optimized for Semiconductor Manufacturing International Corporation (SMIC) 0....
450
1.0
VeriSilicon SMIC 0.13um Syn. LP DROM Compiler, Memory Array Range:128 to 1Mega Bits
VeriSilicon SMIC 0.13um synchronous programmable Low Power diffusion ROM compiler optimized for Semiconductor Manufacturing International Corporation ...