Company
design-reuse.com
D&R China
Blogs
Industry Articles
D&R Events
IP-SoC Days 2025
IP-SoC Days 2024
IP-SoC Days 2023
IP-SoC Days 2022
IP-SoC Days 2021
IP-SoC 2024
IP-SoC 2023
IP-SoC 2022
IP-SoC 2021
Subscribe to D&R SoC News Alert
English
Mandarin
Register
Login
Menu
Home
Search IP Core
News
Blogs
Articles
D&R Events
Subscribe to D&R SoC News Alert
Register
Login
News
Center
Foundation IP
Analog IP
Interface IP
Interconnect IP
Memory Controller
Peripheral Controller
Wireless IP
Wireline IP
Processor IP
RISC-V
AI Core
Automotive IP
Security IP
IoT
Media IP
Avionics / Space IP
Verification IP
Verification Platform
Asic & IP Design Center
IP-SoC Days
IP-SoC Days 2025
IP-SoC Days 2024
IP-SoC Days 2023
IP-SoC Days 2022
IP-SoC Days 2021
IP-SoC 2024
IP-SoC 2023
IP-SoC 2022
IP-SoC 2021
Browse Foundation
Arithmetic & Mathematic (34)
Embedded Memories (1006)
I/O Library (958)
Standard cell (745)
CAM (27)
Diffusion ROM (3)
DRAM (2)
Dual-Port SRAM (22)
EEPROM (30)
Flash Memory (34)
FTP (9)
Metal ROM (1)
MTP (39)
OTP (161)
RAM (286)
Register File (249)
ROM (89)
RRAM (1)
Single-Port SRAM (21)
Via ROM (12)
Other (20)
12-Bit ADC (1)
ESD Protection (69)
General-Purpose I/O (GPIO) (412)
High-speed (137)
LVDS (41)
Memory Interfaces (17)
Special (281)
You must be registered with the D&R website to view the full search results, including:
Complete datasheets for
IP Core
products
Contact information for
IP Core
suppliers
Please
log in
here to your account.
New user ?
Signup here
.
2743 IP
451
1.0
MCU PAD - SMIC 55nm Eflash
...
452
1.0
MCU PAD - SMIC 55nm Eflash
...
453
1.0
MCU PAD - SMIC 55nm Eflash
...
454
1.0
SEC 10nm Multi-Bit Standard Cell Library, 0.45V operation voltage
SEC 10nm 4Multi-Bit Flip-Flop Std Cell Library...
455
1.0
SEC 14nm Multi-Bit Standard Cell Library, 0.5V operation voltage
SEC 14nm 4Multi-Bit Flip-Flop Std Cell Library...
456
1.0
SEC 5nm LVH 6T Multi-Bits Latch
SEC 5nm LVH 6 track High Density Multi-Bits Latch...
457
1.0
VeriSilicon CHRT 0.13um 1.2V/2.5V DUPIO_01 Library
VeriSilicon CHRT 0.13um 1.2V/2.5V DUP I/O Cell Library developed by VeriSilicon is optimized for Chartered Semiconductor Manufacturing (CHRT) 0.13um L...
458
1.0
VeriSilicon CHRT 0.13um 1.2V/3.3V DUPIO_01 Library
VeriSilicon CHRT 0.13um 1.2V/3.3V DUP I/O Cell Library developed by VeriSilicon is optimized for Chartered Semiconductor Manufacturing (CHRT) 0.13um L...
459
1.0
VeriSilicon GSMC 0.18um 1.8v/3v/5v Mult IO for SIMcard
VeriSilicon GSMC 0.18um 1.8V/3.3V Multiple I/O Cell (08) Library developed by VeriSilicon is optimized for Grace Semiconductor Manufacturing Corporati...
460
1.0
VeriSilicon GSMC 0.18um (LP) 1.8V/3.3V Multiple I/O
VeriSilicon GSMC 0.18um (LP) 1.8V/3.3V Multiple I/O Cell (01E) Library developed by VeriSilicon is optimized for Grace Semiconductor Manufacturing Cor...
461
1.0
VeriSilicon GSMC 0.18um 1.8V/3.3V Multiple DUP I/O
VeriSilicon GSMC 0.18μm 1.8V/3.3V Multiple DUP I/O Cell (01E) Library developed by VeriSilicon is optimized for Grace Semiconductor Manufacturing Corp...
462
1.0
VeriSilicon GSMC 0.18um 1.8V/3.3V Multiple I/O (05) Library
VeriSilicon GSMC 0.18um 1.8V/3.3V Multiple I/O Cell (05) Library developed by VeriSilicon is optimized for Grace Semiconductor Manufacturing Corporati...
463
1.0
VeriSilicon GSMC 0.18um General Process, Low Power circuit design, Diffusion ROM
VeriSilicon GSMC 0.18um Synchronous Low Power Diffusion ROM compiler optimized for Grace Semiconductor Manufacturing Corporation (GSMC) 0.18um Logic/A...
464
1.0
VeriSilicon GSMC 0.18um Synchronous Low Power Via1 ROM Compiler, Memory Array Range:128 to 2Mega Bits
VeriSilicon GSMC 0.18um Synchronous Programmable Low Power Via1 ROM compiler optimized for Grace Semiconductor Manufacturing Corporation (GSMC) 0.18um...
465
1.0
VeriSilicon IBM 65nm 1.0V/2.5V VPPIO_01 IO Library
VeriSilicon IBM 65nm 1.0V/2.5V VPPIO_01 IO library developed by VeriSilicon is optimized for IBM 65nm 10sf 1.0/2.5V process. This library provides 6.5...
466
1.0
VeriSilicon SMIC 0.11um 1.2V/3.3V ANALOGIO_DUP_05 IO Library
VeriSilicon SMIC 0.11um 1.2V/3.3V ANALOGIO_DUP_05 IO library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corpo...
467
1.0
VeriSilicon SMIC 0.11μm 1.2V/3.3V DUPIO_01 Library
VeriSilicon SMIC 0.11μm 1.2V/3.3V DUP I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporation...
468
1.0
VeriSilicon SMIC 0.13um 1.2V/2.5V ANALOGIO_DUP_05 IO Library
VeriSilicon SMIC 0.13um 1.2V/2.5V ANALOGIO_DUP_05 IO library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corpo...
469
1.0
VeriSilicon SMIC 0.13um 1.2V/3.3V Multiple DUP I/O Cell
VeriSilicon SMIC 0.13um 1.2V/3.3V Multiple DUP I/O Cell (05) Library developed by VeriSilicon supports power/ground pads, bi-directional I/O, IU (bi-d...
470
1.0
VeriSilicon SMIC 0.13um 1.2V/3.3V Multiple I/O 01C Library
VeriSilicon SMIC 0.13μm 3.3V Multiple I/O 01C Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corpora...
471
1.0
VeriSilicon SMIC 0.13um 1.2V/3.3V Multiple I/O Cell
VeriSilicon SMIC 0.13um 1.2V/3.3V Multiple I/O Cell (05) Library developed by VeriSilicon supports power/ground pads, bi-directional I/O, bidirectiona...
472
1.0
VeriSilicon SMIC 0.13um 1.2V/3.3V Multiple I/O Cell
VeriSilicon SMIC 0.13um 1.2V/3.3V Multiple I/O Cell (06) Library developed by VeriSilicon supports power/ground pads, bi-directional I/O, and input bu...
473
1.0
VeriSilicon SMIC 0.13um 1.2V/3.3V SSTLCOMBO_01 I/O Cell Library
VeriSilicon SMIC 0.13μm SSTL2/SSTL3 Combo I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corpora...
474
1.0
VeriSilicon SMIC 0.13um 1.2V/3.3V SSTLCOMBO_02 I/O Cell Library
VeriSilicon SMIC 0.13μm SSTL2/SSTL18 Combo I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corpo...
475
1.0
VeriSilicon SMIC 0.13um High-Speed Synchronous Single-Port SRAM compiler, Memory Array Range:256 to 128K Bits
VeriSilicon SMIC 0.13um High-Speed Synchronous Single-Port SRAM compiler optimized for Semiconductor Manufacturing International Corporation (SMIC) 0....
476
1.0
VeriSilicon SMIC 0.13um Syn. LP DROM Compiler, Memory Array Range:128 to 1Mega Bits
VeriSilicon SMIC 0.13um synchronous programmable Low Power diffusion ROM compiler optimized for Semiconductor Manufacturing International Corporation ...
477
1.0
VeriSilicon SMIC 0.13um Syn. LP VROM Compiler, Memory Array Range:128 to 1Mega Bits
VeriSilicon SMIC 0.13um Synchronous programmable Low Power Via1 ROM compiler optimized for Semiconductor Manufacturing International Corporation (SMIC...
478
1.0
VeriSilicon SMIC 0.13um Synchronous programmable Via1 ROM compiler,Memory Array Range:128 to 1Mega Bits
VeriSilicon SMIC 0.13um Synchronous programmable Via1 ROM compiler optimized for Semiconductor Manufacturing International Corporation (SMIC) 0.13um L...
479
1.0
VeriSilicon SMIC 0.13um Ultra-Low-Power Synchronous Single-Port SRAM compiler,Memory Array Range:512 to 512K Bits
VeriSilicon SMIC 0.13um Ultra-Low-Power Synchronous Single-Port SRAM compiler optimized for Semiconductor Manufacturing International Corporation (SMI...
480
1.0
VeriSilicon SMIC 0.13umLL 1P3M High-Density Synchronous Single-Port SRAM compiler, Memory Array Range:128 to 512K Bits
VeriSilicon SMIC 0.13umLL 1P3M High-Density Synchronous Single-Port SRAM compiler optimized for Semiconductor Manufacturing International Corporation ...
481
1.0
VeriSilicon SMIC 0.13¦Ìm 1.2V/2.5V DUPIO_01 Library
VeriSilicon SMIC 0.13¦Ìm 1.2V/2.5V DUP I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporatio...
482
1.0
VeriSilicon SMIC 0.13¦Ìm 1.2V/3.3V ANALOGIO_DUP_05 IO Library
VeriSilicon SMIC 0.13um 1.2V/3.3V ANALOGIO_DUP_05 IO library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corpo...
483
1.0
VeriSilicon SMIC 0.13¦Ìm 1.2V/3.3V DUPIO_01 Library
VeriSilicon SMIC 0.13¦Ìm 1.2V/3.3V DUP I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporatio...
484
1.0
VeriSilicon SMIC 0.16um 1.8V/3.3V VPPIO_01 IO Library
VeriSilicon SMIC 0.16um 1.8V/3.3V VPPIO_01 IO library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporation ...
485
1.0
VeriSilicon SMIC 0.18um LL Pro Syn. LP DROM Compiler, Memory Array Range:128 to 2Mega Bits
VeriSilicon SMIC 0.18um Low Leakage Process Synchronous Low Power Diffusion ROM compiler optimized for Semiconductor Manufacturing International Corpo...
486
1.0
VeriSilicon SMIC 0.18um LL Pro Syn. LP VROM Compiler, Memory Array Range:128 to 2Mega Bits
VeriSilicon SMIC 0.18um Low Leakage Process Synchronous Programmable Low Power Via1 ROM compiler optimized for Semiconductor Manufacturing Internation...
487
1.0
VeriSilicon SMIC 0.18um LL Pro. Syn. VROM Compiler, Memory Array Range:128 to 2Mega Bits
VeriSilicon SMIC 0.18um Low Leakage Process Synchronous programmable Via1 ROM compiler optimized for Semiconductor Manufacturing International Corpora...
488
1.0
VeriSilicon SMIC 0.18¦Ìm 1.8V/3.3V ANALOGIO_DUP_05 IO Library
VeriSilicon SMIC 0.18um 1.8V/3.3V ANALOGIO_DUP_05 IO library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corpo...
489
1.0
VeriSilicon SMIC 0.18¦Ìm 1.8V/3.3V VPPIO_DUP_01 IO Library
VeriSilicon SMIC 0.18um 1.8V/3.3V VPPIO_DUP_01 IO library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporat...
490
1.0
VeriSilicon SMIC 0.18μm 1.8V/3.3V ANALOGIO_05 IO Library
VeriSilicon SMIC 0.18um 1.8V/3.3V ANALOGIO_05 IO library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporati...
491
1.0
VeriSilicon SMIC 0.18μm 1.8V/3.3V CFIO_01 Library
VeriSilicon SMIC 0.18μm CF I/O Cell (01) Library developed by VeriSilicon is optimized for SMIC 0.18μm 1P6M Salicide logic process. This library suppo...
492
1.0
VeriSilicon SMIC 0.18µm 1.8V/3.3V VPPIO_01 IO Library
VeriSilicon SMIC 0.18um 1.8V/3.3V VPPIO_01 IO library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporation ...
493
1.0
VeriSilicon TSMC 0.13¦Ìm 1.2V/2.5V DUPIO_01 Library
VeriSilicon TSMC 0.13¦Ìm 1.2V/2.5V DUP I/O Cell Library developed by VeriSilicon is optimized for Taiwan Semiconductor Manufacturing Company (TSMC) 0....
494
1.0
VeriSilicon TSMC 0.13¦Ìm 1.2V/3.3V DUPIO_01 Library
VeriSilicon TSMC 0.13¦Ìm 1.2V/3.3V DUP I/O Cell Library developed by VeriSilicon is optimized for Taiwan Semiconductor Manufacturing Company (TSMC) 0....
495
1.0
VeriSilicon UMC 0.18μm CF I/O
VeriSilicon UMC 0.18μm CF I/O Cell (01) Library developed by VeriSilicon is optimized for UMC 0.18μm 1.8v/3.3v 1P6M Generic II logic process...
496
1.0
VeriSilicon UMC 0.18μm CF I/O
VeriSilicon UMC 0.18μm CF I/O Cell (01) Library developed by VeriSilicon is optimized for UMC 0.18μm 1.8v/3.3v 1P6M Generic II logic process. This lib...
497
1.0
GF 0.13um Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Diffusion ROM Compiler
VeriSilicon CHRT 0.13um High-Speed Synchronous Memory Compiler optimized for Global Foundry 0.13um Logic 1P9M Salicide 1.2/2.5(3.3)V process can flexi...
498
1.0
GF 65nm 1.0V<->3.3V level shifter
GF65nm 1.0V3.3V Level Shfiter Library...
499
1.0
GF 65nm 3.3V Standard Cell Library
GF 65nm 3.3V Standard Cell Library...
500
1.0
HHGrace 0.11um Low Power 7track ECO library
HHGrace 0.11um Low Power 7track ECO Library...
|
Previous
|
10
|
11
|
12
|
...
|
Next
|
