1 10.0

Chip-to-Chip IO Buffer - TSMC CLN4P Analog Bits’ Chip-to-Chip IO Buffer is a general purpose IO for medium-speed per lane transactions in ultra-short reach environments, using single-end...

2 10.0

Chip-to-Chip IO Buffer - TSMC CLN5A Analog Bits’ Chip-to-Chip IO Buffer is a general purpose IO for medium-speed per lane transactions in ultra-short reach environments, using single-end...

3 10.0

Chip-to-Chip IO Buffer - TSMC CLN6FF Analog Bits’ Chip-to-Chip IO Buffer is a general purpose IO for medium-speed per lane transactions in ultra-short reach environments, using single-end...

4 10.0

Chip-to-Chip IO Buffer - TSMC CLN5 Analog Bits’ Chip-to-Chip IO Buffer is a general purpose IO for medium-speed per lane transactions in ultra-short reach environments, using single-end...

5 10.0

Chip-to-Chip IO Buffer - TSMC CLN7FF Analog Bits’ Chip-to-Chip IO Buffer is a general purpose IO for medium-speed per lane transactions in ultra-short reach environments, using single-end...

6 10.0

UCIe based 8-bit 48-Gsps Transceiver (ADC/DAC/PLL/UCIe) Unleash the power of the new UCIe based RF Chiplet transceiver. With NEXT Semiconductor's silicon proven 8-bit, 48-Gsps Transceiver, this product ...

7 14.0

40G Ultralink D2D PHY for Samsung 7LPP Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...

8 14.0

40G Ultralink D2D PHY for GF12LP+ Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...

9 8.0

TSMC CLN5FF Glink 2.0 Die-to-Die PHY IGAD2DY01A is a high speed die-to-die interface PHY which transmits data through TSMC advanced packaging solutions：Integrated Fan-Out (InFO) with RDL ...

10 0.0

TSMC CLN6FF/7FF Die-to-Die Interface PHY This IGAD2DX01A test report shows the functional and characterization test result of GUC Die-to-Die Interface PHY IP for 8 Gbps operation. For IP deta...

11 0.0

TSMC CLN5FF GLink 2.3LL Die-to-Die PHY IGAD2DY04A is a high-speed die-to-die interface PHY which transmits data through TSMC advanced packaging solutions: Integrated Fan-Out (InFO) with RDL...

12 0.0

TSMC CLN5FF GLink GPIO IGID2DY01A GLink GPIO is one of the GLink series IPs. It provides low speed (up to 500 MHz) connection between two dies without requiring any initiali...

13 0.0

TSMC CLN5FF GLink 2.0 Die-to-Die PHY IGPD2DY01A is a high-speed Die-to-Die interface PHY that transmits data through TSMC advanced packaging solutions: Integrated Fan-Out (InFO) with RDL ...

14 0.0

TSMC CLN5FF GLink-3D Die-to-Die Master PHY IGAD2DY02A is a GLink-3D high speed die-to-die interface Master PHY. It is used to transmit data between dies and assembled using TSMC System on Integ...

15 0.0

TSMC CLN7FF GLink-3D Die-to-Die Slave PHY IGAD2DX03A is a GLink-3D high speed die-to-die interface Slave PHY. It is used to transmit data between dies and assembled using TSMC System on Integr...

16 0.0

UCIe PHY on TSMC N3E Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netwo...

17 0.0

UCIe PHY on Samsung SF5A Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netwo...

18 0.0

16G UCIe Standard PHY for TSMC N7 UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...

19 0.0

16G UCIe Standard PHY for TSMC N5A Automotive UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...

20 0.0

16G UCIe Standard PHY for TSMC N4P UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...

21 0.0

16G UCIe Standard PHY for TSMC N3A Automotive UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...

22 0.0

16G UCIe Standard PHY for Samsung SF5A UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...

23 0.0

16G UCIe Advanced PHY for TSMC N3P UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...

24 0.0

16G UCIe Advanced PHY for TSMC N4P/N5P UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...

25 0.0

32G UCIe Standard PHY for TSMC N3P UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...

26 0.0

40G Ultralink D2D PHY for TSMC N6, N7 Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...

27 0.0

40G Ultralink D2D PHY for TSMC N5P Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...

28 0.0

40G Ultralink D2D PHY for TSMC N3P Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...

29 5.0556

UF16 D2D: <4Gbps low-power die-to-die interface, TSMC 16nm A silicon-proven, low-power die-to-die interface in TSMC 16nm (FFC/FFC+) for flip-chip / multi-die assembly. Separate TX-only and RX-only cells run in...

30 8.5077

UCIe 2.0 PHY for Standard Package (5nm) The UCI Express Specification Revision 2.0 supports high-speed serialization and deserialization at 4GT/s, 8GT/s, 12GT/s, and 16GT/s with a 16-lane co...

31 8.5077

UCIe 2.0 PHY for Advanced Package (4nm) The UCI Express Specification Revision 2.0 supports high-speed serialization and deserialization at 4GT/s, 8GT/s, 12GT/s, 16GT/s, 24GT/s and 32GT/s wi...

32 0.0

XSR PHY for TSMC N5 The Synopsys USR/XSR PHY IP for 112Gbps per lane die-to-die connectivity enables high-bandwidth ultra and extra short reach interfaces in multi-chip m...

33 100.0

UCIe-S PHY for Standard Package (x16) in Samsung (SF5A, SF4X, SF2) Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...

34 100.0

UCIe-S PHY for Standard Package (x16) in TSMC (N7, N6, N4P, N5, N3) Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...

35 100.0

UCIe-A PHY for Advanced Package (x64) in TSMC (N7, N6, N5, N3) Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...

36 10.0

Die-to-Die, 112G Ultra-Extra Short Reach PHY in TSMC (12nm, N7, N6, N5) The Synopsys XSR PHY IP for 112Gbps per lane die-to-die connectivity enables high-bandwidth ultra and extra short reach interfaces in multi-chip modul...

37 10.0

Die-to-Die, 112G Ultra-Extra Short Reach PHY in GF (12nm) The Synopsys XSR PHY IP for 112Gbps per lane die-to-die connectivity enables high-bandwidth ultra and extra short reach interfaces in multi-chip modul...

38 0.0

UCIe-A PHY for Advanced Package (x64) in Samsung (SF4X) Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...

39 0.0

UCIe-A PHY for Advanced Package (x64) in TSMC (N5) Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...

40 0.0

UCIe-A PHY for Advanced Package (x64) in Samsung (SF2) Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...

41 0.0

UCIe-S PHY for Standard Package (x32) in TSMC (N3P) Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...

42 0.0

UCIe PHY IP on TSMC N3P Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...

43 70.0

40G UCIe PHY IP on Samsung SF4X Synopsys UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale data center, AI,...

44 9.0308

UCIe 2.0 PHY for Standard Package (8nm) The UCI Express Specification Revision 2.0 supports high-speed serialization and deserialization at 4GT/s, 8GT/s, 12GT/s, 16GT/s, and 24GT/s with a 64...

45 8.5077

UCIe 2.0 PHY for Advanced Package (8nm) The UCI Express Specification Revision 2.0 supports high-speed serialization and deserialization at 4GT/s, 8GT/s, 12GT/s, 16GT/s, and 24GT/s with a 64...

46 0.0

Interface Controller - PHY IP The UCIE PHY IP is a market leading, extremely low-power, low-latency interface IP for very high bandwidth connections between two dies that are on th...

47 0.0

UCIe Standard Package PHY on Samsung S8LPU The UCIE PHY IP is a market leading, extremely low-power, low-latency interface IP for very high bandwidth connections between two dies that are on th...

48 0.0

UCIe Standard Package PHY on Samsung S14LPP The UCIE PHY IP is a market leading, extremely low-power, low-latency interface IP for very high bandwidth connections between two dies that are on th...

49 8.5077

UCIe 2.0 PHY for Standard Package (4nm) The UCI Express Specification Revision 2.0 supports high-speed serialization and deserialization at 4GT/s, 8GT/s, 12GT/s, and 16GT/s with a 16-lane co...

50 0.0

UCIe-S (Gen2) Compatible PHY for Standard Package (x16) in TSMC (N3P) Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...