Design & Reuse
Catalog of SIP Cores
System on Chip design resources
2 IP
1
0.0
Ultra-low-power Processor based on RISC-V
The icyflex-V is a next-generation ultra-low-power 32-bit processor core developed by CSEM, based on the RISC-V RV32IMC instruction set architecture. ...
2
0.0
RPU-REFLEX-RV — RISC-V Reflexive Energy Layer
A drop-in reflexive hardware layer for RISC-V cores (Ibex, CV32E40P). Connects to irq_external_i — CPU enters WFI sleep, wakes in exactly 2 clock cycl...