Design & Reuse
Catalog of SIP Cores
System on Chip design resources
704 IP
701
0.0
Synopsys HBM3 PHY IP on N7
The Synopsys HBM3 PHY is a complete physical layer IP interface (PHY) solution for high-performance computing (HPC), AI, graphics, and networking ASIC...
702
0.0
Synopsys LPDDR Controller for LPDDR6, LPDDR5X and LPDDR5
Synopsys LPDDR6/5X/5 Controller IP is a next generation controller optimized for power, latency, bandwidth, and area, supporting JEDEC standard LPDDR6...
703
0.0
Synopsys LPDDR6/5X/5 PHY IP for TSMC N2P
The Synopsys LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performance LPDDR6, LP...
704
0.0
Synopsys LPDDR6/5X/5 PHY IP for TSMC N3P
The Synopsys LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performance LPDDR6, LP...