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Browse Memory Controller & PHY
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666 IP
251
0.118
DDR2/3 Controller IP, DDR2/3 controller with DFI 2.1 interfaces, Support DDR1/DDR2/DDR3 SDRAM, Soft IP
DDR2/3 Combo SDRAM Controller....
252
0.118
DDR2/3 PHY Combo PHY data block (1.0v SP & 2.5V device); UMC 90nm SP/RVT LowK Logic Process
DDR2/3 PHY Combo PHY data block (1.0v SP & 2.5V device); UMC 90nm SP/RVT LowK Logic Process...
253
0.118
DDR2/DDR1/MDDR Combo Command/Address Block ; UMC 65nm LP/RVT LowK Logic Process
DDR2/DDR1/MDDR Combo Command/Address Block ; UMC 65nm LP/RVT LowK Logic Process...
254
0.118
DDR2/DDR1/MDDR Combo Data Block ; UMC 65nm LP/RVT LowK Logic Process
DDR2/DDR1/MDDR Combo Data Block ; UMC 65nm LP/RVT LowK Logic Process...
255
0.118
DDR2/MDDR Combo Command/Address Block ; UMC 0.13um HS/FSG Logic Process
DDR2/MDDR Combo Command/Address Block ; UMC 0.13um HS/FSG Logic Process...
256
0.118
DDR2/MDDR Combo Data Block ; 0.13um Logic HS/FSG Logic Process
DDR2/MDDR Combo Data Block ; 0.13um Logic HS/FSG Logic Process...
257
0.118
DDR2/MDDR Combo PHY CMD ADDR block ; UMC 55nm SP/RVT Lowk Process with 2.5V device
DDR2/MDDR Combo PHY CMD ADDR block ; UMC 55nm SP/RVT Lowk Process with 2.5V device...
258
0.118
DDR2/MDDR Combo PHY data block ; UMC 55nm SP process with 2.5V device
DDR2/MDDR Combo PHY data block ; UMC 55nm SP process with 2.5V device...
259
0.118
DDR2/MDDR COMBO PHY Data block for Chip usage ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process
DDR2/MDDR COMBO PHY Data block for Chip usage ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process...
260
0.118
DDR2/MDDR Combo PHY for Chip load usage ; UMC 65NM SP-RVT with 2.5V device LowK Logic Process
DDR2/MDDR Combo PHY for Chip load usage ; UMC 65NM SP-RVT with 2.5V device LowK Logic Process...
261
0.118
DDR2/MDDR PHY CMD/ADDR BLOCK ; UMC 65nm 1.0V process with 2.5V device SP/RVT Lowk Logic Process
DDR2/MDDR PHY CMD/ADDR BLOCK ; UMC 65nm 1.0V process with 2.5V device SP/RVT Lowk Logic Process...
262
0.118
DDR2/MDDR PHY CMD/ADDR BLOCK for DIMM usage ; UMC 65nm 1.0V with 2.5V Device SP/RVT LowK Logic Process
DDR2/MDDR PHY CMD/ADDR BLOCK for DIMM usage ; UMC 65nm 1.0V with 2.5V Device SP/RVT LowK Logic Process...
263
0.118
DDR2/MDDR PHY CMD/ADDR BLOCK for DIMM usage; UMC 55nm 1.0V with 2.5V device SP/RVT LowK Logic Process
DDR2/MDDR PHY CMD/ADDR BLOCK for DIMM usage; UMC 55nm 1.0V with 2.5V device SP/RVT LowK Logic Process...
264
0.118
DDR2/MDDR PHY Data block ; UMC 65nm 1.0V with 2.5V device SP/RVT LowK Logic Process
DDR2/MDDR PHY Data block ; UMC 65nm 1.0V with 2.5V device SP/RVT LowK Logic Process...
265
0.118
DDR23 COMBO PHY CMD/ADDR BLOCK ; UMC 40LP/RVT LowK Logic Process with 2.5V device
DDR23 COMBO PHY CMD/ADDR BLOCK ; UMC 40LP/RVT LowK Logic Process with 2.5V device...
266
0.118
DDR23 COMBO PHY CMD/ADDR BLOCK ; UMC 40LP/RVT LowK Logic Process with 2.5V device for 2 layer PCB board usage
DDR23 COMBO PHY CMD/ADDR BLOCK ; UMC 40LP/RVT LowK Logic Process with 2.5V device for 2 layer PCB board usage...
267
0.118
DDR23 COMBO PHY compensation Block ; UMC 40LP/RVT LowK Logic Process with 2.5V device
DDR23 COMBO PHY compensation Block ; UMC 40LP/RVT LowK Logic Process with 2.5V device...
268
0.118
DDR23 COMBO PHY Data Block ; UMC 40nm LP/RVT LowK Logic Process with 2.5V device
DDR23 COMBO PHY Data Block ; UMC 40nm LP/RVT LowK Logic Process with 2.5V device...
269
0.118
DDR23 COMBO PHY Data Block ; UMC 40nm LP/RVT LowK Logic Process with 2.5V device (16Bit)
DDR23 COMBO PHY Data Block ; UMC 40nm LP/RVT LowK Logic Process with 2.5V device (16Bit)...
270
0.118
DDR3 Combo PHY COMM/ADDR Block for 2-rank and solder bump application; UMC 40nm LP/RVT Logic Process
DDR3 Combo PHY COMM/ADDR Block for 2-rank and solder bump application; UMC 40nm LP/RVT Logic Process...
271
0.118
DDR3 Combo PHY COMM/ADDR Block for 2-rank and solder bump application; UMC 40nm LP/RVT Logic Process
DDR3 Combo PHY COMM/ADDR Block for 2-rank and solder bump application; UMC 40nm LP/RVT Logic Process...
272
0.118
DDR3 Combo PHY Compensation Block for solder bump application; UMC 40nm LP/RVT Logic Process
DDR3 Combo PHY Compensation Block for solder bump application; UMC 40nm LP/RVT Logic Process...
273
0.118
DDR3 Combo PHY Data Block for solder bump application; UMC 40nm LP/RVT Logic Process
DDR3 Combo PHY Data Block for solder bump application; UMC 40nm LP/RVT Logic Process...
274
0.118
DDR3 RTL Digitalize PHY AC block; UMC 28nm HPC/RVT Logic Process using FSJ0C_ARS
DDR3 RTL Digitalize PHY AC block; UMC 28nm HPC/RVT Logic Process using FSJ0C_ARS...
275
0.118
DDR3 RTL Digitalize PHY DATA block; UMC 28nm HPC/RVT Logic Process using FSJ0C_ARS
DDR3 RTL Digitalize PHY DATA block; UMC 28nm HPC/RVT Logic Process using FSJ0C_ARS...
276
0.118
DDR3 RTL PHY Address Command module
DDR3 RTL PHY Address Command module...
277
0.118
DDR3 RTL PHY data module
DDR3 RTL PHY data module...
278
0.118
DDR3/2 COMBO PHY CMD/ADDR BLOCK for 2 layer 8 bits DDR3 PCB ; UMC 40LP/RVT LowK Logic Process with 2.5V device
DDR3/2 COMBO PHY CMD/ADDR BLOCK for 2 layer 8 bits DDR3 PCB ; UMC 40LP/RVT LowK Logic Process with 2.5V device...
279
0.118
DDR3/2 COMBO PHY DATA BLOCK for 2 layer 8 bits DDR3 PCB ; UMC 40LP/RVT LowK Logic Process with 2.5V device
DDR3/2 COMBO PHY DATA BLOCK for 2 layer 8 bits DDR3 PCB ; UMC 40LP/RVT LowK Logic Process with 2.5V device...
280
0.118
DDR3/DDR3L/LPDDR2 combo PHY ( not support DDR3 leveling function), command / address block,UMC 40nm LP/RVT LowK Logic Process.
DDR3/DDR3L/LPDDR2 combo PHY ( not support DDR3 leveling function), command / address block,UMC 40nm LP/RVT LowK Logic Process....
281
0.118
DDR3/DDR3L/LPDDR2 combo PHY ( not support DDR3 leveling function), data block;UMC 40nm LP/RVT LowK Logic Process .
DDR3/DDR3L/LPDDR2 combo PHY ( not support DDR3 leveling function), data block;UMC 40nm LP/RVT LowK Logic Process ....
282
0.118
DDR34 COMBO PHY ADDR Block for Solder bump Flip chip version ;UMC 40nm LP/RVT Logic Process
DDR34 COMBO PHY ADDR Block for Solder bump Flip chip version ;UMC 40nm LP/RVT Logic Process...
283
0.118
DDRII Data Block for Chip Application; UMC 0.11um HS/AE (AL Advance Enhancement) Logic Process
DDRII Data Block for Chip Application; UMC 0.11um HS/AE (AL Advance Enhancement) Logic Process...
284
0.118
DDRII Data Block for Chip Application; UMC 0.13um HS/FSG Logic Process
DDRII Data Block for Chip Application; UMC 0.13um HS/FSG Logic Process...
285
0.118
DDRx Bist Controller with I2C slave and multi-channel AMBA master
DDRx Bist Controller with I2C slave and multi-channel AMBA master...
286
0.118
DFI Wrapper
DFI Wrapper...
287
0.118
DFI3.1 Wrapper for DDR3/DDR4/LPDDR2/LPDDR3 PHY
DFI3.1 Wrapper for DDR3/DDR4/LPDDR2/LPDDR3 PHY...
288
0.118
UMC 40nm LP process DDR34/LPDDR23 COMPENSATION Block with 2.5V Device
UMC 40nm LP process DDR34/LPDDR23 COMPENSATION Block with 2.5V Device...
289
0.118
UMC 55NM SP-RVT with 2.5V device DDR23 COMBO PHY CMD/ADDR Block for 2 layer PCB board usage
UMC 55NM SP-RVT with 2.5V device DDR23 COMBO PHY CMD/ADDR Block for 2 layer PCB board usage...
290
0.118
UMC 55NM SP-RVT with 2.5V device process 16BIT DDR23 COMBO DATA PHY for two layer PCB board usage
UMC 55NM SP-RVT with 2.5V device process 16BIT DDR23 COMBO DATA PHY for two layer PCB board usage...
291
0.118
Combo DDR34/LPDDR23 Controller with 8 ports AHB/AXI interfaces
Combo DDR34/LPDDR23 Controller with 8 ports AHB/AXI interfaces...
292
0.118
Command/address block of 1:2 DDR2-PHY ; 0.11um HS/AE (AL Advanced Enhancement) Logic Process
Command/address block of 1:2 DDR2-PHY ; 0.11um HS/AE (AL Advanced Enhancement) Logic Process...
293
0.118
Command/Address Block of DDR3 Combo PHY for DIMM version ; UMC 55nm LP/RVT LowK Logic Process
Command/Address Block of DDR3 Combo PHY for DIMM version ; UMC 55nm LP/RVT LowK Logic Process...
294
0.118
Command/Address Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process
Command/Address Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process...
295
0.118
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant to DFI); UMC 55nm SP/RVT LowK Logic Process
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant to DFI); UMC 55nm SP/RVT LowK Logic Process...
296
0.118
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant with DFI spec); UMC 40nm LP LowK Logic Process
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant with DFI spec); UMC 40nm LP LowK Logic Process...
297
0.118
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process...
298
0.118
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process...
299
0.118
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process...
300
0.118
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application;UMC 55nm SP/RVT LowK PROCESS.
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application;UMC 55nm SP/RVT LowK PROCESS....
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