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Browse Memory Controller & PHY
DDR (649)
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DDR Controller (51)
DDR PHY (365)
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365 IP
1
100.0
TSMC CLN4P 4nm DDR5 PHY - 6400Mbps
The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individ...
2
40.0
LPDDR5/4x/4 combo PHY on 14nm, 12nm
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
3
28.0
LPDDR4x Secondary/Slave (memory side!) PHY
This LPDDR4X PHY is a memory-side interface IP normally found implemented within commodity DRAM products. Green Mountain Semiconductor's LPDDR4X IP pr...
4
28.0
LPDDR4x/5 Secondary/Slave (memory side!) PHY
This LPDDR4/4X/5 PHY is a memory-side interface IP normally found implemented within commodity DRAM products. Green Mountain Semiconductor's LPDDR4X/L...
5
28.0
LPDDR5 Secondary/Slave (memory side!) PHY
This LPDDR5 PHY is a memory-side interface IP normally found implemented within commodity DRAM products. Green Mountain Semiconductor's LPDDR5 IP prov...
6
28.0
LPDDR5X Secondary/Slave (memory side!) PHY
This LPDDR5X PHY is a memory-side interface IP normally found implemented within commodity DRAM products. Green Mountain Semiconductor's LPDDR5X IP pr...
7
20.0
LPDDR4 multiPHY V2 in Samsung (14nm, 11nm, 10nm, 8nm)
The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...
8
20.0
LPDDR4 multiPHY V2 in TSMC (28nm, 22nm, 16nm, 12nm)
The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...
9
20.0
LPDDR4X multiPHY in Samsung (14nm, 11nm)
The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...
10
20.0
LPDDR4X multiPHY in TSMC (16nm, 12nm,N7, N6)
The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...
11
20.0
LPDDR4x/4 PHY IP for 22nm
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
12
20.0
LPDDR5X/5/4X PHY in Samsung (SF4X, SF2)
The Synopsys LPDDR5X/5/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system- in- package...
13
20.0
LPDDR5X/5/4X/4 combo PHY at 12nm
The LPDDR5X/5/4X/4 combo PHY IP features a state-of-art mixed-signal architecture that addresses the challenges of DRAM integration in high-performan...
14
20.0
LPDDR5X/5/4X/4 PHY for 16nm
The LPDDR5X/5/4X/4 combo PHY IP features a state-of-art mixed-signal architecture that addresses the challenges of DRAM integration in high-performan...
15
15.0
HBM3 PHY IP at 7nm
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
16
15.0
GDDR6 PHY IP for 12nm
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
17
15.0
LPDDR5X/5/4X/4 PHY IP for 12nm
The LPDDR5X/5/4X/4 combo PHY IP features a state-of-art mixed-signal architecture that addresses the challenges of DRAM integration in high-performan...
18
11.0
DDR5/4 PHY & Controller
DDR5/4 PHY & Controller...
19
11.0
LPDDR5/5X PHY & Controller
High performance, low power and area efficient memory interface solutions conforming to LPDDR5/5X (JESD209-5C) JEDEC standard...
20
10.0
DDR4/3 PHY in Samsung (14nm, 11nm, 10nm, 8nm)
The Synopsys DDR4/3 PHY is a complete physical layer IP interface (PHY) solution for enterprise-class ASIC, ASSP, and system-on-chip (SoC) application...
21
10.0
DDR4/3 PHY in TSMC (12nm, 16nm, 7nm)
The Synopsys DDR4/3 PHY is a complete physical layer IP interface (PHY) solution for enterprise-class ASIC, ASSP, and system-on-chip (SoC) application...
22
10.0
DDR5 PHY in Samsung (SF2, SF4X)
The Synopsys DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-...
23
10.0
DDR5/4 PHY in Samsung (10nm, 8nm, 7nm)
The Synopsys DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-...
24
5.0
DDR3/4 and LPDDR2/3/4/4x Combo PHY&MAC
With sophisticated architecture and advanced technology, this DDR3/4 and LPDDR2/3/4/4x IP combo solution with high performance and low power. In 12~28...
25
5.0
DDR4/LPDDR4/LPDDR4X PHY
M31 LPDDR4X multi-PHY supports both LPDDR4 and LPDDR4X memory interfaces at speed up to 4267Mbps, making it an ideal solution for ASICS, ASSPs, SOC an...
26
5.0
DDR4IO for memory PHY, 3200Mbps
The DDR4 IO is used to transfer the Command/Address/Clk and Data between the memory controller PHY and the DRAM device. The TX is designed to send inf...
27
4.0
DDR3/DDR4 IP solution with high performance and low power
With sophisticated architecture and advanced technology, KNiulink provide DDR3/DDR4 IP solution with high performance and low power. KNiulink could o...
28
3.0
LPDDR2/3/4/4x IP combo solution with high performance and low power
With sophisticated architecture and advanced technology, this LPDDR2/3/4/4x IP combo solution with high performance and low power. In 12~28nm CMOS pro...
29
1.0
GDDR7 PHY & Controller
The INNOSILICON™ GDDR7 PHY is fully compliant with the JEDEC GDDR7 standard, supporting data rates of up to 32 Gbps in PAM3 mode. In PAM3 mode, each b...
30
1.0
DDR3/3L/2 Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal DDR3/3L/2 COMBO PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible S...
31
1.0
DDR3/3L/2/LPDDR3/2 Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal DDR3/3L/2/LPDDR3/2 COMBO PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC com...
32
1.0
DDR4/3 Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal DDR4/3 COMBO PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDRA...
33
1.0
DDR4/3/2 Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal DDR4/3/2 PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDRAM de...
34
1.0
DDR4/3/3L/LPDDR3 Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal DDR4/3/3L/LPDDR3 COMBO PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC compa...
35
1.0
DDR4/3/LPDDR3 Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal DDR4/3/LPDDR3 COMBO PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC compatib...
36
1.0
DDR4/3/LPDDR4/3 Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal DDR4/3/LPDDR4/4X/3 COMBO PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC com...
37
1.0
DDR4/3/LPDDR4X/4/3 Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal DDR4/3/LPDDR4/4X/3 COMBO PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC com...
38
1.0
DDR4/LPDDR4/3 Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal DDR4/LPDDR4/3 COMBO PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC compatib...
39
1.0
DDR4/LPDDR4/4X/3 Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal DDR4/LPDDR4/4X/3 COMBO PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC compa...
40
1.0
DDR4/LPDDR4X/4 Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal LPDDR4/4X/DDR4 PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible SD...
41
1.0
INNOLINK Chiplet PHY&Controller
Innosilicon INNOLINK™ IP provides a leading-edge chiplet solution allowing massive amounts of low-latency data to pass seamlessly between smaller chi...
42
1.0
INNOLINK-B Controller
The INNOLINK Controller (ILC) combined with INNOLINK PHY is a complete solution for high speed data communication between dies or chips. INNOLIN, GDDR...
43
1.0
INNOLINK-B PHY
Innosilicon can provide different Die2Die solution for customer depend on package type, Following is Innosilicon Die2Die IP family: Innolink-A, Serde...
44
1.0
INNOLINK-C Controller
The INNOLINK-C Controller (hereinafter referred to as “ILC”) combined with INNOLINK-C PHY is a complete solution for high-speed data communication bet...
45
1.0
INNOLINK-C PHY
Innosilicon can provide different Die-to-Die and Chip-to-Chip solutions for customer according to package types. The followings are Innosilicon Die-to...
46
1.0
LPDDR2 PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal LPDDR2 PHY provides turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDRAM devi...
47
1.0
LPDDR3/2 Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal LPDDR3/2 COMBO PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible SD...
48
1.0
LPDDR3/2/DDR3/3L Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal LPDDR2/3/DDR3/3L COMBO PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC compa...
49
1.0
LPDDR3/2/DDR3/3L/2 Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal LPDDR3/2/DDR3/3L/2 COMBO PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC com...
50
1.0
LPDDR4X/4 Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal LPDDR4 PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDRAM devi...
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