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arrow SDIO Controller (3)
arrow SDRAM Controller (107)
arrow SRAM Controller (3)
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901 IP
51
20.0
112Gbps Serdes USR & XSR
With sophisticated architecture and advanced technology, KNL multi-mode D2D transceiver IP with PMA and PCS layer is designed for low power and high p...
52
20.0
32/64-bit PC133 SDRAM Controller
The 32/64-bit PC133 SDRAM Controller” controller handles PC133 SDRAM compatible memory devices attached to a 32 or 64 bit wide data bus. The cont...
53
20.0
HBM3 PHY (Hard 1) in TSMC (N6, N5)
The Synopsys HBM3 PHY is a complete physical layer IP interface (PHY) solution for high-performance computing (HPC), AI, graphics, and networking ASIC...
54
20.0
HBM3 PHY in TSMC (N5, N6, N7)
The Synopsys HBM3 PHY is a complete physical layer IP interface (PHY) solution for high-performance computing (HPC), AI, graphics, and networking ASIC...
55
20.0
UHS-II PHY
Silicon Library's world-first silicon proven UHS-II PHY supporting 1.56Gbps speed is available in various fabs/nodes, including TSMC6/12/40/85, GF28, ...
56
20.0
eMMC 5.1 Host Controller
The eMMC 5.1 Host Controller IP from Arasan Chip Systems is a highly integrated host controller IP solution. This IP handles all of the timing and ...
57
20.0
Combo SerDes PHY
With sophisticated architecture and advanced technology, KNiulink multi-mode transceiver IP with PMA and PCS layer is designed for low power and high ...
58
20.0
LPDDR4 multiPHY V2 in GF (22nm)
The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...
59
20.0
LPDDR4 multiPHY V2 in Samsung (14nm, 11nm, 10nm, 8nm)
The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...
60
20.0
LPDDR4 multiPHY V2 in TSMC (28nm, 22nm, 16nm, 12nm)
The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...
61
20.0
LPDDR4X multiPHY in GF (14nm)
The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...
62
20.0
LPDDR4X multiPHY in Samsung (14nm, 11nm)
The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...
63
20.0
LPDDR4X multiPHY in TSMC (16nm, 12nm,N7, N6)
The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...
64
20.0
LPDDR4X multiPHY Plus in GF (12nm)
The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...
65
20.0
LPDDR4x/4 PHY IP for 22nm
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
66
20.0
LPDDR5/4/4X PHY in GF (12nm)
The Synopsys LPDDR5/4/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system- in-package a...
67
20.0
LPDDR5/4/4X PHY in TSMC (16nm, 12nm, N7, N6, N5)
The Synopsys LPDDR5/4/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system- in-package a...
68
20.0
LPDDR5/4x/4 PHY IP for Samsung 14LPU
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
69
20.0
LPDDR5X/5/4X PHY in Samsung (SF4X, SF2)
The Synopsys LPDDR5X/5/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system- in- package...
70
20.0
LPDDR5X/5/4X/4 combo PHY at 12nm
The LPDDR5X/5/4X/4 combo PHY IP features a state-of-art mixed-signal architecture that addresses the challenges of DRAM integration in high-performan...
71
20.0
LPDDR5X/5/4X/4 PHY for 16nm
The LPDDR5X/5/4X/4 combo PHY IP features a state-of-art mixed-signal architecture that addresses the challenges of DRAM integration in high-performan...
72
20.0
xSPI Flash Memory Controller
The xSPI-MC core is a versatile serial flash memory controller, which allows a system to easily detect and access the attached flash device or directl...
73
20.0
CXL memory expansion
DenseMem increases effective CXL Type 3 Device memory capacity by a factor of 2x through transparent, in-line memory compression/decompression with mi...
74
15.0
HBM3 PHY IP at 7nm
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
75
15.0
HBM3E Controller
Bandwidth and area optimized low power memory interface solution tuned for AI, HPC, data centers and networking conforming to HBM3 JEDEC standards...
76
15.0
GDDR6 PHY IP for 12nm
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
77
15.0
High Bandwidth Memory 3 (HBM3/3E) IP optimized for Samsung SF4X
SkyeChip’s HBM3 IP consists of a PHY and memory controller optimized for Samsung SF4X process to support the HBM3 memory standard (JESD238A) operating...
78
15.0
LPDDR5X/5/4X/4 PHY IP for 12nm
The LPDDR5X/5/4X/4 combo PHY IP features a state-of-art mixed-signal architecture that addresses the challenges of DRAM integration in high-performan...
79
14.0
NAND Flash Controller
Cadence IP Controller for ONFI NAND and Toggle NAND NAND Flash memory is widely used for data storage in computers and multiple consumer and enterpri...
80
14.0
GDDR6 PHY for Samsung
High-performance IP for graphics, AI/ML, and automotive products The latest, the Denali PHY IP for GDDR6, is comprised of architectural improvements ...
81
14.0
DDR2/DDR3/DDR3L/LPDDR/LPDDR2/LPDDR3 6 in one combo IO with auto calibration - 40nm LL
DDR2/DDR3/DDR3L/LPDDR/LPDDR2/LPDDR3 6 in one combo IO with auto calibration in 40nm LL...
82
14.0
DDR3/LPDDR23 PHY - 55LL
B55LLDDRPHY-D3LP23 IP is compliant to JESD79-3F(DDR3), JESD209-2F(LPDDR2), JESD209-3B(LPDDR3),DFI3.1 specification and delivers an unbeatable combinat...
83
14.0
DDR3/LPDDR23 PHY - 65LL
B65LLDDRPHY-D3LP23 IP is compliant to JESD79-3F(DDR3), JESD209-2F(LPDDR2), JESD209-3B(LPDDR3),DFI3.1 specification and delivers an unbeatable combinat...
84
14.0
DDR34/LPDDR23 PHY - 40LL
B40LLDDRPHY-D34LP23 IP is compliant to JESD79-3F(DDR3), JESD79-4A(DDR4), JESD209-2F(LPDDR2), JESD209-3B(LPDDR3),DFI3.1 specification and delivers an u...
85
14.0
DDR34/LPDDR34 PHY - 28HK
B28HKDDRPHY-D34LP34 IP is compliant to JESD79-3F(DDR3), JESD79-4A(DDR4), JESD209-3B(LPDDR3), JESD209-4A (LPDDR4), DFI3.1 specification and delivers an...
86
14.0
Denali Controller for DDR
LPDDR5/4X/4/3 and DDR5/4/3L/3, to 6400Mbps and beyond The Cadence Denali Controller IP for LPDDR5/4X/4/3 and DDR5/4/3L/3 provides low latency and up ...
87
14.0
Denali Controller for GDDR6
GDDR6 devices to 16Gbps, 18Gbps, 20Gbps, and beyond The latest, the Cadence Denali Controller IP for GDDR6, provides low latency and very high bandwi...
88
14.0
Denali DDR PHY for TSMC
LPDDR4/3, DDR4/3/3L, up to 4266Mbps The latest Denali high-speed DDR PHY IP is comprised of architectural improvements to its highly successful prede...
89
14.0
Denali High-Speed DDR PHY for UMC
Provides the industry's highest data rates with low-latency througput while balancing power consumption and minimizing area Developed by experienced ...
90
11.0
HBM3 PHY & Controller
SkyeChip’s High Bandwidth Memory (HBM) IP consists of a PHY and memory controller optimized for TSMC N7, N12 and Samsung 4nm process to support the HB...
91
11.0
DDR5/4 PHY & Controller
DDR5/4 PHY & Controller...
92
11.0
LPDDR5/5X PHY & Controller
High performance, low power and area efficient memory interface solutions conforming to LPDDR5/5X (JESD209-5C) JEDEC standard...
93
10.0
NAND Flash Memory Controller with DMA
NANDFCTRL2 is a VHDL IP core implementing an interface to NAND flash memory devices. The core supports ONFI 4.0 and provides DMA transfers to and from...
94
10.0
HBM3 Controller IP is optimized for power, latency, bandwidth, and area, supporting the JEDEC HBM3 standard
Synopsys HBM3 Controller IP is optimized for power, latency, bandwidth, and area, supporting the JEDEC HBM3 standard. The controller interoperates wit...
95
10.0
SD 3.0 / SDIO 3.0 Combo Device Controller
The SD / SDIO 3.0 Combo Device IP Core is a high performance controller capable of interfacing with memory cards and I/O applications such as WLAN, Bl...
96
10.0
SD 4.0 Device Controller
The SD 4.0 Device IP core is used to implement SD cards connected to a Host processor over standard SD bus. The flexible architecture of SD Device IP ...
97
10.0
SD/eMMC in GF (12nm)
To address today’s content capacity and bandwidth requirements, JEDEC and SD Association continue to define new functionality and enhancements for emb...
98
10.0
SD/eMMC in TSMC (28nm, 16nm, 12nm, N7, N6)
To address today’s content capacity and bandwidth requirements, JEDEC and SD Association continue to define new functionality and enhancements for emb...
99
10.0
DDR and LPDDR 5/4/3/2 controllers for low power and high Reliability, Availability and Serviceability (RAS)
Synopsys offers a complete system-level memory interface IP portfolio for SoCs requiring an interface to one or a range of high-performance DDR5, DDR4...
100
10.0
DDR2/DDR3/DDR3L/LPDDR2 I/O Buffer - TSMC 40 CLN40LP
Analog Bits impedance programmable I/O buffer provides a high-speed physical interface solution to support the increasing bandwidths demanded by today...