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arrow SRAM/SDRAM Controller (112)
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931 IP
501
0.118
UMC 55NM SP-RVT with 2.5V device process 16BIT DDR23 COMBO DATA PHY for two layer PCB board usage
UMC 55NM SP-RVT with 2.5V device process 16BIT DDR23 COMBO DATA PHY for two layer PCB board usage...
502
0.118
ONFI PHY Compensation Block for ONFI4.0 application; UMC 40nm LP/RVT Logic Process
ONFI PHY Compensation Block for ONFI4.0 application; UMC 40nm LP/RVT Logic Process...
503
0.118
Combo DDR34/LPDDR23 Controller with 8 ports AHB/AXI interfaces
Combo DDR34/LPDDR23 Controller with 8 ports AHB/AXI interfaces...
504
0.118
Command/address block of 1:2 DDR2-PHY ; 0.11um HS/AE (AL Advanced Enhancement) Logic Process
Command/address block of 1:2 DDR2-PHY ; 0.11um HS/AE (AL Advanced Enhancement) Logic Process...
505
0.118
Command/Address Block of DDR3 Combo PHY for DIMM version ; UMC 55nm LP/RVT LowK Logic Process
Command/Address Block of DDR3 Combo PHY for DIMM version ; UMC 55nm LP/RVT LowK Logic Process...
506
0.118
Command/Address Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process
Command/Address Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process...
507
0.118
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant to DFI); UMC 55nm SP/RVT LowK Logic Process
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant to DFI); UMC 55nm SP/RVT LowK Logic Process...
508
0.118
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant with DFI spec); UMC 40nm LP LowK Logic Process
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant with DFI spec); UMC 40nm LP LowK Logic Process...
509
0.118
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process...
510
0.118
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process...
511
0.118
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process...
512
0.118
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application;UMC 55nm SP/RVT LowK PROCESS.
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application;UMC 55nm SP/RVT LowK PROCESS....
513
0.118
Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for Solder bump Flip chip version ; UMC 40nm LP LowK Logic Process
Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for Solder bump Flip chip version ; UMC 40nm LP LowK Logic Process...
514
0.118
Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY supporting 2-rank application for Copper Pillar Bump Flip Chip Version; UMC 40nm LP LVT/RVT LowK Logic Process
Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY supporting 2-rank application for Copper Pillar Bump Flip Chip Version; UMC 40nm LP LVT/RVT...
515
0.118
Compact Flash host interface controller with APB interface.
...
516
0.118
compensation block for FXDDR3LTA102HH0L and FXDDR3LTD102HH0L,UMC 40nm LP/RVT LowK Logic Process .
compensation block for FXDDR3LTA102HH0L and FXDDR3LTD102HH0L,UMC 40nm LP/RVT LowK Logic Process ....
517
0.118
Compensation Block of DDR3 Combo PHY for DIMM version ; UMC 55nm LP/RVT LowK Logic Process
Compensation Block of DDR3 Combo PHY for DIMM version ; UMC 55nm LP/RVT LowK Logic Process...
518
0.118
Compensation Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process
Compensation Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process...
519
0.118
Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for SIP Application; UMC 28nm HPC/RVT LowK Logic Process
Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for SIP Application; UMC 28nm HPC/RVT LowK Logic Process...
520
0.118
Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for SIP Application; UMC 28nm HPC/RVT LowK Logic Process; Vertical version
Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for SIP Application; UMC 28nm HPC/RVT LowK Logic Process; Vertical version...
521
0.118
Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY; UMC 55nm LP/RVT LowK Logic Process
Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY; UMC 55nm LP/RVT LowK Logic Process...
522
0.118
Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY; UMC 55nm SP/RVT LowK Logic Process
Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY; UMC 55nm SP/RVT LowK Logic Process...
523
0.118
LPDDR3-PHY Command/address block for LightCo ; UMC 40nm LP/RVT Logic Process
LPDDR3-PHY Command/address block for LightCo ; UMC 40nm LP/RVT Logic Process...
524
0.118
SRAM/ROM Controller IP, SRAM/ROM Controller, Soft IP
Static memory controller with AXI interface....
525
0.0
NAND flash Controller using Altera PHY Lite
IP-Maker's Universal NAND Flash Controller (UNFC) IP core is designed specifically to enable commodity Flash memory to be effectively used in enterpri...
526
0.0
NAND Flash Controller using Xilinx RX/TX Bit Slice
IP-Maker's Universal NAND Flash Controller (UNFC) IP core is designed specifically to enable commodity Flash memory to be effectively used in enterpri...
527
0.0
HBM Memory Controller
Produced by DRAM manufacturers such as Samsung and Micron, High Bandwidth Memory or HBM, provides users with high bandwidth, low power consumption and...
528
0.0
HBM2 Controller IP
SmartDV’s HBM2 (High Bandwidth Memory) Controller IP delivers high-speed, low-latency access to stacked DRAM, making it an ideal solution for AI, HPC,...
529
0.0
HBM2 Memory Controller
HBM2 Memory Controller...
530
0.0
HBM2/2E Memory Controller Core
The Rambus HBM2/2E Controller Core is designed for use in applications requiring high memory throughput, low latency and full programmability. The ...
531
0.0
HBM2E Controller IP
HBM2E is full-featured, easy-to-use, synthesizable design, compatible with HBM2E JESD235B and JESD235C with revision 4.10 specification and DFI-versio...
532
0.0
HBM2E Memory Controller
HBM2E Memory Controller...
533
0.0
HBM3 Controller IP
SmartDV’s HBM3 Controller IP delivers a high-bandwidth, low-latency memory interface solution tailored for high-performance computing, AI/ML accelerat...
534
0.0
HBM3 Memory Controller
HBM3 Memory Controller...
535
0.0
HBM3 PHY IP for TSMC N4
The Synopsys HBM3 PHY is a complete physical layer IP interface (PHY) solution for high-performance computing (HPC), AI, graphics, and networking ASIC...
536
0.0
HBM3 PHY IP for TSMC N7
The Synopsys HBM3 PHY is a complete physical layer IP interface (PHY) solution for high-performance computing (HPC), AI, graphics, and networking ASIC...
537
0.0
HBM3 PHY IP on TSMC N5
The Synopsys HBM3 PHY is a complete physical layer IP interface (PHY) solution for high-performance computing (HPC), AI, graphics, and networking ASIC...
538
0.0
HBM3 PHY on TSMC N3P
The Synopsys HBM3 PHY is a complete physical layer IP interface (PHY) solution for high-performance computing (HPC), AI, graphics, and networking ASIC...
539
0.0
UCIe Chiplet PHY & Controller in Global Foundries (12 nm, 14 nm)
INNOSILICON™ UCIe Chiplet IP offers a customizable solution for seamless, low-latency data transfer between silicon dies and chips, enabling heterogen...
540
0.0
UCIe Chiplet PHY & Controller in Samsung (8nm, 10nm, 14nm)
INNOSILICON™ UCIe Chiplet IP offers a customizable solution for seamless, low-latency data transfer between silicon dies and chips, enabling heterogen...
541
0.0
UCIe Chiplet PHY & Controller in SMIC (14 nm)
INNOSILICON™ UCIe Chiplet IP offers a customizable solution for seamless, low-latency data transfer between silicon dies and chips, enabling heterogen...
542
0.0
UCIe Chiplet PHY & Controller in TSMC (3nm, 4nm, 5nm, 7nm, 10nm, 12nm, 16nm)
INNOSILICON™ UCIe Chiplet IP offers a customizable solution for seamless, low-latency data transfer between silicon dies and chips, enabling heterogen...
543
0.0
SD 5.1 / eMMC 5.1 Host Controller IP
Our Host IP is specially designed to combo both SD eMMC features. SD feature: The Secure Digital (SD) Card, supports SD5.1 and later specifications...
544
0.0
SD UHS-II PHY IP
SLI PSDUHS2A_PHY is PHY IP solution for UHS-II interface that SD Association is working on the standardization as the new ultra high speed interface f...
545
0.0
SD UHS-III PHY (UHS-II Gen2) IP
SLIPSDUHS3A_PHY is PHY IP solution for UHS-II interface that SD Association is working on the standardization as the new ultra high speed interface fo...
546
0.0
SD/SDIO Device Controller
A compact low power and scalable IP core which provides a simple, firmware-friendly cost-effective Physical Link interface for memory, i/o and combo d...
547
0.0
GDDR2 Controller IP
GDDR2 interface provides full support for the GDDR2 interface, compatible with GDDR2 specification and DFI-version 4.0 or 5.0 Specification Compliant....
548
0.0
GDDR3 Controller IP
GDDR3 interface provides full support for the GDDR3 interface, compatible with GDDR3 specification and DFI-version 4.0 or 5.0 Specification Compliant....
549
0.0
GDDR3L Controller IP
GDDR3L interface provides full support for the GDDR3L interface, compatible with GDDR3L specification and DFI-version 4.0 or 5.0 Specification Complia...
550
0.0
GDDR4 Controller IP
GDDR4 interface provides full support for the GDDR4 interface, compatible with GDDR4Spec_rev_04 specification and DFI-version 4.0 or 5.0 Specification...