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931 IP
601
0.0
DDR4/3/3L/LPDDR3 Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal DDR4/3/3L/LPDDR3 COMBO PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC compa...
602
0.0
DDR4/3/LPDDR3 Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal DDR4/3/LPDDR3 COMBO PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC compatib...
603
0.0
DDR4/3/LPDDR4/3 Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal DDR4/3/LPDDR4/4X/3 COMBO PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC com...
604
0.0
DDR4/3/LPDDR4X/4/3 Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal DDR4/3/LPDDR4/4X/3 COMBO PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC com...
605
0.0
DDR4/LPDDR4/3 Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal DDR4/LPDDR4/3 COMBO PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC compatib...
606
0.0
DDR4/LPDDR4/4X/3 Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal DDR4/LPDDR4/4X/3 COMBO PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC compa...
607
0.0
DDR4/LPDDR4X/4 Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal LPDDR4/4X/DDR4 PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible SD...
608
0.0
DDR5 PHY&MAC - high performance and low power
With sophisticated architecture and advanced technology, KNiulink provide DDR5 with high performance and low power. In advanced process nodes, KNiuli...
609
0.0
DDR5 CKD 01 - Clock Driver
The DDR5CKD01 is a registering clock driver used on DDR5 CUDIMMs, CSODIMMs, and CAMM. Its primary function is to buffer the DDR clock between the Host...
610
0.0
DDR5 Controller IP
SmartDV’s DDR5 Controller IP is a high-performance solution designed to meet the demands of next-generation memory systems in computing, networking, a...
611
0.0
DDR5 Memory Controller IP with Advanced Feautures
DDR5 is full-featured, easy-to-use, synthesizable design, compatible with DDR5 JESD79-5 and JESD79-5 Rev1.40 (Draft) specification and DFI-version 5.0...
612
0.0
DDR5 Memory PHY for Samsung SF5A Automotive
Provides the industry's highest data rates with low-latency througput while balancing power consumption and minimizing area The latest, the DDR5 PH...
613
0.0
DDR5 Memory PHY for TSMC N3P
Provides the industry's highest data rates with low-latency througput while balancing power consumption and minimizing area The latest, the DDR5 PH...
614
0.0
DDR5 Memory PHY for TSMC N4P
Provides the industry's highest data rates with low-latency througput while balancing power consumption and minimizing area The latest, the DDR5 PH...
615
0.0
DDR5 Memory PHY for TSMC N5P
Provides the industry's highest data rates with low-latency througput while balancing power consumption and minimizing area The latest, the DDR5 PH...
616
0.0
DDR5 MRDIMM2 PHY in TSMC (N3P, N2P)
The Synopsys DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-...
617
0.0
DDR5 PHY for SS SF4X
The Synopsys DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-...
618
0.0
DDR5 PHY IP for TSMC N3P
The Synopsys DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-...
619
0.0
DDR5 Power Management IC
Power Management IC (PMIC) is designed for DDR5 RDIMM, DDR5 LRDIMM, DDR5 NVDIMM application. PMIC is used for switching and LDO regulators. PMIC-I3C I...
620
0.0
DDR5 REGISTERING CLOCK DRIVER (RCD) IP - DDR5RCD03
The DDR5RCD03 is a registering clock driver used on DDR5 RDIMMs and LRDIMMs. Its primary function is to buffer the Command/Address (CA) bus, chip sele...
621
0.0
DDR5 Serial Presence Detect (SPD5) Hub Interface
The SPD5 Hub Function IP has been developed to interface I3C/I2C Host Bus and it allows an isolation of local devices like Temperature Sensor(TS), fro...
622
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DDR5 Temperature Sensor - TS5111 and TS5110
he TS5111 and TS5110 device incorporate thermal sensing capability which is controlled and read over two wire bus. These device operate on I2C and I3C...
623
0.0
DDR5/4 COMBO PHY 7nm/6nm
The DDR5/4 Combo PHY is designed for easy integration into any System-On-Chip (SOC) and can be seamlessly connected with a third-party DFI-compliant D...
624
0.0
DDR5/4 COMBO PHY U22
The DDR5/4 Combo PHY is designed for easy integration into any System-On-Chip (SOC) and can be seamlessly connected with a third-party DFI-compliant D...
625
0.0
DDR5/4 Memory PHY for Samsung SF5A Automotive
Provides the industry's highest data rates with low-latency througput while balancing power consumption and minimizing area The latest, the DDR5/4 ...
626
0.0
DDR5/4 Memory PHY for TSMC 16nm
Provides the industry's highest data rates with low-latency througput while balancing power consumption and minimizing area The latest, the DDR5/4 ...
627
0.0
DDR5/4 Memory PHY for TSMC N7
Provides the industry's highest data rates with low-latency througput while balancing power consumption and minimizing area The latest, the DDR5/4 ...
628
0.0
DDR5/4 PHY for Samsung 7LPP
Provides the industry's highest data rates with low-latency througput while balancing power consumption and minimizing area The latest, the DDR5/4 ...
629
0.0
DDR5/4/LPDDR5/4X PHY for TSMC for N5P
Lowest latency and highest data rates for data-intensive applications Developed by experienced teams with industry-leading domain expertise and ext...
630
0.0
DDR5/DDR4/LPDDR5 Combo PHY IP - 4800Mbps (Silicon Proven in TSMC 12FFC)
The DDR PHY IP supports DDR5/ DDR4/ LPDDR5, provides low latency, and enables up to 5400MT/s throughput. PHY functionality is verified in NC-Verilog s...
631
0.0
Read-Modify-Write Core
The Read-Modify-Write (RMW) Core from Rambus handles misaligned bursts when an Error Correction Code (ECC) is being used. An ECC code word must be ca...
632
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Reorder Core
The Reorder Core from Rambus reorders requests based on first on priority and second on throughput optimization. Throughput optimization includes m...
633
0.0
DFI LPDDR5 PHY IP
DFI LPDDR5 is full-featured, easy-to-use, synthesizable design, compatible with LPDDR5 JESD209-5 specification and DFI-version 5.0 Compliant. Through ...
634
0.0
AGILEX 7 R-Tile NVME HOST IP
Gen5 NVMe Host IP on AGILEX7 R-Tile It enables random access, sequential access, Read/Write access and multi-user access. To show these features, s...
635
0.0
AHB Parallel Flash Controller
The AHB Parallel Flash Controller allows an AHB Master (usually a CPU) to read, program, or erase the connected arrangement of external parallel Super...
636
0.0
AHB SRAM Controller
The AHB SRAM Controller provides a standard AHB interface to translate AHB bus reads and writes into reads and writes with the signaling and timing of...
637
0.0
High Bandwidth Memory (HBM2E) HBM2E PHY for Global Foundries 12nm
Optimized for the low-latency and high-bandwidth memory applications, the HBM Gen2 PHY delivers maximum performance and flexibility HBM is a high-p...
638
0.0
High Bandwidth Memory (HBM2E) HBM2E PHY for Samsung 11nm
Optimized for high bandwidth and low latency, the HBM2E PHY delivers maximum performance and flexibility in a compact form factor HBM2E is a high-p...
639
0.0
High Bandwidth Memory (HBM2E) HBM2E PHY for TSMC N7
Optimized for the low-latency and high-bandwidth memory applications, the HBM Gen2 PHY delivers maximum performance and flexibility HBM is a high-p...
640
0.0
High Bandwidth Memory (HBM3E) 3 PHY for TSMC N3P
Designed for performance and low latency in AI/ML, HPC, data center and graphics applications The High-Bandwidth Memory generation 3 (HBM3E) PHY is...
641
0.0
High Bandwidth Memory (HBM3E) 3 PHY for TSMC N5P
Designed for performance and low latency in AI/ML, HPC, data center and graphics applications The High-Bandwidth Memory generation 3 (HBM3E) PHY is...
642
0.0
High Bandwidth Memory (HBM3E) 3 PHY for TSMC N7
Designed for performance and low latency in AI/ML, HPC, data center and graphics applications The High-Bandwidth Memory generation 3 (HBM3) PHY is ...
643
0.0
High Performance DDR 3/2 Memory Controller IP
This memory controller supports DDR2/3 SDRAM. DDR2/3 memory controller is a high-speed interface used for data read/write between internal engine and ...
644
0.0
Single Port SRAM Compiler IP, 4.0um2 bit cells, Synchronous high density, UMC 0.18um HV process
UMC 0.18um high voltage 1.8V process synchronous high density Single Port SRAM memory compiler....
645
0.0
Single, Dual and Quad SPI Flash Controller with Boot and Execute On-The-Fly Features
The SPI-MEM-CTRL core from Alma Technologies offers the interconnection between a host and an SPI Flash memory device. The SPI-MEM-CTRL supports Singl...
646
0.0
MMC Target Controller
A compact low power and scalable IP core which provides a simple, firmware-friendly cost-effective Physical Link interface for MultiMediaCard-based m...
647
0.0
eMMC 5.1 HS400 PHY and I/O Pads in TSMC 16FF PLUS
Arasan provides a HS400 compatible PHY that customers can integrate with the HS400 I/O PADs. It is designed to optimize I/O performance with a core v...
648
0.0
eMMC Device Controller
eMMC 5.1 IP fully compliant to JEDEC JESD-84-B51, supporting full backwards compatibility, high speed SDR, high speed DDR, HS200 and HS400 transfer mo...
649
0.0
eMMC Device IP
SmartDV’s eMMC (embedded MultiMediaCard) Device IP is a silicon-proven, high-performance solution designed for embedded storage applications across mo...
650
0.0
eMMC Host IP
SmartDV’s eMMC (embedded MultiMediaCard) Host IP is a silicon-proven solution tailored for high-performance storage interfaces in mobile, automotive, ...