Design & Reuse
Catalog of SIP Cores
System on Chip design resources
983 IP
651
0.0
DDR5 MRDIMM for Intel
Lowest latency and highest data rates for data-intensive applications Cadence Design IP solutions offer world-class DDR PHY and controller memory I...
652
0.0
DDR5 MRDIMM2 PHY in Samsung (SF2P)
The Synopsys DDR5 MRDIMM2 PHY IP is part of a complete IP solution including PHY and Controller enabling ASIC, Application-specific standard products ...
653
0.0
DDR5 MRDIMM3 PHY in TSMC (N2P)
The Synopsys DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-...
654
0.0
DDR5 PHY for SS SF4X
The Synopsys DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-...
655
0.0
DDR5 PHY IP for TSMC N3P
The Synopsys DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-...
656
0.0
DDR5 REGISTERING CLOCK DRIVER (RCD) IP - DDR5RCD03
The DDR5RCD03 is a registering clock driver used on DDR5 RDIMMs and LRDIMMs. Its primary function is to buffer the Command/Address (CA) bus, chip sele...
657
0.0
DDR5/4 COMBO PHY 7nm/6nm
The DDR5/4 Combo PHY is designed for easy integration into any System-On-Chip (SOC) and can be seamlessly connected with a third-party DFI-compliant D...
658
0.0
DDR5/4 COMBO PHY U22
The DDR5/4 Combo PHY is designed for easy integration into any System-On-Chip (SOC) and can be seamlessly connected with a third-party DFI-compliant D...
659
0.0
DDR5/4 Memory PHY for Samsung SF5A Automotive
Provides the industry's highest data rates with low-latency througput while balancing power consumption and minimizing area The latest, the DDR5/4 ...
660
0.0
DDR5/4 Memory PHY for TSMC 16nm
Provides the industry's highest data rates with low-latency througput while balancing power consumption and minimizing area The latest, the DDR5/4 ...
661
0.0
DDR5/4 Memory PHY for TSMC N7
Provides the industry's highest data rates with low-latency througput while balancing power consumption and minimizing area The latest, the DDR5/4 ...
662
0.0
DDR5/4 PHY for Samsung 7LPP
Provides the industry's highest data rates with low-latency througput while balancing power consumption and minimizing area The latest, the DDR5/4 ...
663
0.0
DDR5/4/LPDDR5/4X PHY for TSMC for N5P
Lowest latency and highest data rates for data-intensive applications Developed by experienced teams with industry-leading domain expertise and ext...
664
0.0
DDR5/DDR4/LPDDR5 Combo PHY IP - 4800Mbps (Silicon Proven in TSMC 12FFC)
The DDR PHY IP supports DDR5/ DDR4/ LPDDR5, provides low latency, and enables up to 5400MT/s throughput. PHY functionality is verified in NC-Verilog s...
665
0.0
Read-Modify-Write Core
The Read-Modify-Write (RMW) Core from Rambus handles misaligned bursts when an Error Correction Code (ECC) is being used. An ECC code word must be ca...
666
0.0
Reorder Core
The Reorder Core from Rambus reorders requests based on first on priority and second on throughput optimization. Throughput optimization includes m...
667
0.0
DFI LPDDR5 PHY IP
DFI LPDDR5 is full-featured, easy-to-use, synthesizable design, compatible with LPDDR5 JESD209-5 specification and DFI-version 5.0 Compliant. Through ...
668
0.0
AHB Parallel Flash Controller
The AHB Parallel Flash Controller allows an AHB Master (usually a CPU) to read, program, or erase the connected arrangement of external parallel Super...
669
0.0
AHB SRAM Controller
The AHB SRAM Controller provides a standard AHB interface to translate AHB bus reads and writes into reads and writes with the signaling and timing of...
670
0.0
High Bandwidth Memory (HBM2E) HBM2E PHY for Global Foundries
Optimized for high bandwidth and low latency, the HBM2E PHY delivers maximum performance and flexibility in a compact form factor. HBM is a high-pe...
671
0.0
High Bandwidth Memory (HBM2E) HBM2E PHY for Global Foundries 12nm
Optimized for the low-latency and high-bandwidth memory applications, the HBM Gen2 PHY delivers maximum performance and flexibility HBM is a high-p...
672
0.0
High Bandwidth Memory (HBM2E) HBM2E PHY for Samsung
Optimized for high bandwidth and low latency, the HBM2E PHY delivers maximum performance and flexibility in a compact form factor. HBM2E is a high-...
673
0.0
High Bandwidth Memory (HBM2E) HBM2E PHY for Samsung 11nm
Optimized for high bandwidth and low latency, the HBM2E PHY delivers maximum performance and flexibility in a compact form factor HBM2E is a high-p...
674
0.0
High Bandwidth Memory (HBM2E) HBM2E PHY for TSMC
Optimized for high bandwidth and low latency, the HBM2E PHY delivers maximum performance and flexibility in a compact form factor. HBM is a high-pe...
675
0.0
High Bandwidth Memory (HBM2E) HBM2E PHY for TSMC N7
Optimized for the low-latency and high-bandwidth memory applications, the HBM Gen2 PHY delivers maximum performance and flexibility HBM is a high-p...
676
0.0
High Bandwidth Memory (HBM3E) 3 PHY for TSMC N3P
Designed for performance and low latency in AI/ML, HPC, data center and graphics applications The High-Bandwidth Memory generation 3 (HBM3E) PHY is...
677
0.0
High Bandwidth Memory (HBM3E) 3 PHY for TSMC N5P
Designed for performance and low latency in AI/ML, HPC, data center and graphics applications The High-Bandwidth Memory generation 3 (HBM3E) PHY is...
678
0.0
High Bandwidth Memory (HBM3E) 3 PHY for TSMC N7
Designed for performance and low latency in AI/ML, HPC, data center and graphics applications The High-Bandwidth Memory generation 3 (HBM3) PHY is ...
679
0.0
High Bandwidth Memory (HBM4E) PHY for Rapidus
Designed for performance and low latency in AI/ML, HPC, data center and graphics applications The High-Bandwidth Memory generation (HBM4/4E) PHY is...
680
0.0
High Performance DDR 3/2 Memory Controller IP
This memory controller supports DDR2/3 SDRAM. DDR2/3 memory controller is a high-speed interface used for data read/write between internal engine and ...
681
0.0
Single Port SRAM Compiler IP, 4.0um2 bit cells, Synchronous high density, UMC 0.18um HV process
UMC 0.18um high voltage 1.8V process synchronous high density Single Port SRAM memory compiler....
682
0.0
Single, Dual and Quad SPI Flash Controller with Boot and Execute On-The-Fly Features
The SPI-MEM-CTRL core from Alma Technologies offers the interconnection between a host and an SPI Flash memory device. The SPI-MEM-CTRL supports Singl...
683
0.0
Single-port 16/32/64-bit DDR266 Controller
The Single-port 16/32/64 bit DDR266 controller IP core is a DDR266 SDRAM controller AMBA AHB back-end. The controller can interface two 16-, 32- or 64...
684
0.0
MMC Target Controller
A compact low power and scalable IP core which provides a simple, firmware-friendly cost-effective Physical Link interface for MultiMediaCard-based m...
685
0.0
eMMC 5.1 HS400 PHY and I/O Pads in TSMC 16FF PLUS
Arasan provides a HS400 compatible PHY that customers can integrate with the HS400 I/O PADs. It is designed to optimize I/O performance with a core v...
686
0.0
eMMC Device Controller
eMMC 5.1 IP fully compliant to JEDEC JESD-84-B51, supporting full backwards compatibility, high speed SDR, high speed DDR, HS200 and HS400 transfer mo...
687
0.0
eMMC Device IP
SmartDV’s eMMC (embedded MultiMediaCard) Device IP is a silicon-proven, high-performance solution designed for embedded storage applications across mo...
688
0.0
eMMC Host IP
SmartDV’s eMMC (embedded MultiMediaCard) Host IP is a silicon-proven solution tailored for high-performance storage interfaces in mobile, automotive, ...
689
0.0
eMMC/SD/SDIO PHY & Controller
INNOSILICON™ eMMC/SD/SDIO Combo IP is a comprehensive solution designed to support high-performance storage and I/O connectivity for a wide range of a...
690
0.0
ONFI
INNOSILICON™ ONFI IP provides a connectivity solutions for ICs requiring access to ONFI-compatible NAND Flash devices. Optimized for low-power and hig...
691
0.0
ONFI 4.0 NAND Flash PHY upto 800Mbps
...
692
0.0
ONFI 4.1 PHY IP (Silicon Proven in TSMC 12FFC)
ONFI PHY block is used to either transmit signal and data to NAND Flash interface or receive the data from NAND Flash by Flash controller IP. MDLL set...
693
0.0
ONFI 5.1 3,600MT/s PHY, 28nm, 12nm and 7nm
The EGIS ONFI PHY is a mass production-proven, high-performance ONFI PHY IP designed to meet the stringent requirements of next-generation NAND Flash ...
694
0.0
ONFI 6.0 4,800MT/s PHY IP on 7nm and 6nm
The InPsytech ONFI 4,800 PHY is a silicon-proven, high-performance ONFI PHY IP designed to meet the stringent requirements of next-generation NAND Fla...
695
0.0
ONFi PHY 4.0 (FPHY+MDLL+SDLL Regulator) (Silicon Proven in TSMC 28HPC+)
ONFI PHY block is used to either transmit signal and data to NAND Flash interface, or receive the data from NAND Flash by Flash controller IP. MDLL se...
696
0.0
INNOLINK Chiplet PHY&Controller
Innosilicon INNOLINK™ IP provides a leading-edge chiplet solution allowing massive amounts of low-latency data to pass seamlessly between smaller chi...
697
0.0
INNOLINK-B Controller
The INNOLINK Controller (ILC) combined with INNOLINK PHY is a complete solution for high speed data communication between dies or chips. INNOLIN, GDDR...
698
0.0
INNOLINK-B PHY
Innosilicon can provide different Die2Die solution for customer depend on package type, Following is Innosilicon Die2Die IP family: Innolink-A, Serde...
699
0.0
INNOLINK-C Controller
The INNOLINK-C Controller (hereinafter referred to as “ILC”) combined with INNOLINK-C PHY is a complete solution for high-speed data communication bet...
700
0.0
INNOLINK-C PHY
Innosilicon can provide different Die-to-Die and Chip-to-Chip solutions for customer according to package types. The followings are Innosilicon Die-to...