Design & Reuse
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arrow SRAM/SDRAM Controller (112)
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931 IP
651
0.0
eMMC/SD/SDIO PHY & Controller
INNOSILICON™ eMMC/SD/SDIO Combo IP is a comprehensive solution designed to support high-performance storage and I/O connectivity for a wide range of a...
652
0.0
ONFI
INNOSILICON™ ONFI IP provides a connectivity solutions for ICs requiring access to ONFI-compatible NAND Flash devices. Optimized for low-power and hig...
653
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ONFI 4.0 NAND Flash PHY upto 800Mbps
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654
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ONFI 4.1 PHY IP (Silicon Proven in TSMC 12FFC)
ONFI PHY block is used to either transmit signal and data to NAND Flash interface or receive the data from NAND Flash by Flash controller IP. MDLL set...
655
0.0
ONFI 5.1 3,600MT/s PHY, 28nm, 12nm and 7nm
The EGIS ONFI PHY is a mass production-proven, high-performance ONFI PHY IP designed to meet the stringent requirements of next-generation NAND Flash ...
656
0.0
ONFI 6.0 4,800MT/s PHY IP on 7nm and 6nm
The InPsytech ONFI 4,800 PHY is a silicon-proven, high-performance ONFI PHY IP designed to meet the stringent requirements of next-generation NAND Fla...
657
0.0
ONFi PHY 4.0 (FPHY+MDLL+SDLL Regulator) (Silicon Proven in TSMC 28HPC+)
ONFI PHY block is used to either transmit signal and data to NAND Flash interface, or receive the data from NAND Flash by Flash controller IP. MDLL se...
658
0.0
INNOLINK Chiplet PHY&Controller
Innosilicon INNOLINK™ IP provides a leading-edge chiplet solution allowing massive amounts of low-latency data to pass seamlessly between smaller chi...
659
0.0
INNOLINK-B Controller
The INNOLINK Controller (ILC) combined with INNOLINK PHY is a complete solution for high speed data communication between dies or chips. INNOLIN, GDDR...
660
0.0
INNOLINK-B PHY
Innosilicon can provide different Die2Die solution for customer depend on package type, Following is Innosilicon Die2Die IP family: Innolink-A, Serde...
661
0.0
INNOLINK-C Controller
The INNOLINK-C Controller (hereinafter referred to as “ILC”) combined with INNOLINK-C PHY is a complete solution for high-speed data communication bet...
662
0.0
INNOLINK-C PHY
Innosilicon can provide different Die-to-Die and Chip-to-Chip solutions for customer according to package types. The followings are Innosilicon Die-to...
663
0.0
Up to 50% main memory bandwidth acceleration
The Ziptilion Bandwidth IP accelertes the main memory bandwidth with up to 50%. The IP core packages a novel and proprietary technology that accelerat...
664
0.0
LPDDR Controller for LPDDR5X, LPDDR5 and LPDDR4X
Synopsys LPDDR5X/5/4X Controller is a next generation controller optimized for power, latency, bandwidth, and area, supporting JEDEC standard LPDDR5X,...
665
0.0
LPDDR Controller IP
LPDDR is full-featured, easy-to-use, synthesizable design, compatible with JESD209A-1 and JESD209B specification. Through its LPDDR compatibility, it ...
666
0.0
LPDDR2 Controller IP
LPDDR2 interface provides full support for the LPDDR2 interface, compatible with JESD209-2E and JESD209-2F specification. Through its LPDDR2 compatibi...
667
0.0
LPDDR2 PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal LPDDR2 PHY provides turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDRAM devi...
668
0.0
LPDDR3 Controller IP
SmartDV’s LPDDR3 Controller IP offers a high-performance and low-latency solution for integrating LPDDR3 memory interfaces into SoCs and FPGA-based sy...
669
0.0
LPDDR3/2 Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal LPDDR3/2 COMBO PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible SD...
670
0.0
LPDDR3/2/DDR3/3L Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal LPDDR2/3/DDR3/3L COMBO PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC compa...
671
0.0
LPDDR3/2/DDR3/3L/2 Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal LPDDR3/2/DDR3/3L/2 COMBO PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC com...
672
0.0
LPDDR4 Controller IP
SmartDV’s LPDDR4 Controller IP is a high-performance solution designed to enable fast, power-efficient memory access in mobile, automotive, and high-p...
673
0.0
LPDDR4 multiPHY V2 in UMC (28nm)
The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...
674
0.0
LPDDR4/ DDR4/ DDR3L PHY IP - 1866Mbps (Silicon Proven in TSMC 28HPC+)
The LPDDR4/ DDR4/ DDR3L Combo PHY IP offers low latency and supports throughput of up to 1866Mbps. The PHY IP is silicon validated in the TSMC 28HPC+ ...
675
0.0
LPDDR4/DDR4/DDR3 PHY - TSMC 22nmULL
SP-LPD4/D43_PHY16BIT-T22ULL is designed for DRAM controller to connect to the LPDDR4/DDR4/3 DRAM memory device. It contains a DDR PHY Control Unit(DPC...
676
0.0
LPDDR4X / LPDDR4 Controller
The Rambus LPDDR4X/4 controller core is designed for use in applications requiring high memory throughput at low power including mobile, Internet of ...
677
0.0
LPDDR4X, LPDDR4, DDR4, LPDDR3 Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal LPDDR4/4X/DDR4/LPDDR3 PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC compat...
678
0.0
LPDDR4X/4/3/DDR4 PHY for TSMC 12nm and 16nm
Lowest latency and highest data rates for data-intensive applications Developed by experienced teams with industry-leading domain expertise and ext...
679
0.0
LPDDR4X/4/3/DDR4/3/3L PHY + Controller
INNOSILICON™ LPDDR4X/4/3/DDR4/3/3L Combo IP is a customizable Mixed-Signal DDR memory interface suite. The Combo IP provides turnkey physical interfac...
680
0.0
LPDDR5 Controller IP
SmartDV’s LPDDR5 Controller IP delivers high-bandwidth, low-latency memory access optimized for next-generation mobile, automotive, and AI/ML applicat...
681
0.0
LPDDR5 IP - High performance and low power
With sophisticated architecture and advanced technology, KNiulink provide LPDDR5 with high performance and low power. In advanced process nodes, KNiu...
682
0.0
LPDDR5/4/4X Controller with Inline Memory Encryption (IME) Security Module
SynopsysLPDDR5/4/4X Controller is a next generation controller optimized for power, latency, bandwidth, and area, supporting JEDEC standard LPDDR5, LP...
683
0.0
LPDDR5/4X COMBO PHY 7nm/6nm
The LPDDR5 and LPDDR4x Combo PHY is designed for easy integration into any System-On-Chip (SOC) and can be seamlessly connected with a third-party DFI...
684
0.0
LPDDR5/4X PHY IP for TSMC N7
Lowest latency and highest data rates for data-intensive applications The LPDDR PHY IP is comprised of architectural improvements to its highly suc...
685
0.0
LPDDR5/4x/4 PHY IP for Samsung 14LPU
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
686
0.0
LPDDR5/5X Memory PHY for TSMC N3P
Lowest latency and highest data rates for data-intensive applications The LPDDR PHY IP is comprised of architectural improvements to its highly suc...
687
0.0
LPDDR5/5X Memory PHY for TSMC N4P
Lowest latency and highest data rates for data-intensive applications The LPDDR PHY IP is comprised of architectural improvements to its highly suc...
688
0.0
LPDDR5/5X Memory PHY for TSMC N5P
Lowest latency and highest data rates for data-intensive applications The LPDDR PHY IP is comprised of architectural improvements to its highly suc...
689
0.0
LPDDR5X 7nm/6nm PHY
The InPsytech LPDDR5x PHY is a high-performance, low-power physical interface IP designed for seamless integration into any System-on-Chip (SoC). It c...
690
0.0
LPDDR5X Controller IP
LPDDR5X is full-featured, easy-to-use, synthesizable design, compatible with LPDDR5X draft JEDEC specification and DFI-version 5.0 specification Compl...
691
0.0
LPDDR5X PHY 3nm
The InPsytech LPDDR5x PHY is a high-performance, low-power physical interface IP designed for seamless integration into any System-on-Chip (SoC). It c...
692
0.0
LPDDR5X PHY 5nm/4nm
The InPsytech LPDDR5x PHY is a high-performance, low-power physical interface IP designed for seamless integration into any System-on-Chip (SoC). It c...
693
0.0
LPDDR5x/5 Driver SDK Starter Kit
The MOUNT MUIR LPDDR5x (MM-LPDDR5x) solution is a comprehensive SDK that enables users to easily implement functions and interface with LPDDR5X Memory...
694
0.0
LPDDR5x/5 IP Subystem (Processing Engine+Memory Controller+PHY+VIP+TestCases)
MEMTECH’ LPDDR5X (Low Power DDR5X) complete IP Subsystem is optimized to accelerate LPDDR5x IP subsystem development, minimize the subsystem integrati...
695
0.0
LPDDR5x/5 Synthesizable Verification IP
MEMTECH’ GT LPDDR5x/5 VIP is optimized for fast debug & system validation to help you reach highest memory performance resulting in lower time to trai...
696
0.0
LPDDR5x/5 SystemC TLM Cycle Accurate Model
MEMTECH’ Mount Stanford-L series LPDDR5x Memory Controller SystemC Model can support customers with high-performance simulation model needs. This stan...
697
0.0
LPDDR5X/5/4X COMBO PHY
The LPDDR5x, LPDDR5, and LPDDR4x Combo PHY is designed for seamless integration into any System-on-Chip (SoC) and can easily connect to a third-party ...
698
0.0
LPDDR5X/5/4X Controller with Inline Memory Encryption (IME) Security Module
Synopsys LPDDR5X/5/4X Controller is a next generation controller optimized for power, latency, bandwidth, and area, supporting JEDEC standard LPDDR5X,...
699
0.0
LPDDR5X/5/4X PHY IP on TSMC N3P
The Synopsys LPDDR5X/5/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system- in- package...
700
0.0
LPDDR6, LPDDR5X Combo PHY & Controller
The INNOSILICON™ DDR IP delivers a JEDEC-compliant LPDDR6/5X/5 Combo PHY and Controller, optimized for next-generation low-power, high-speed applicati...