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Browse Memory Controller & PHY
DDR (705)
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SRAM/SDRAM Controller (112)
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DDR Controller (319)
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NAND Flash PHY (13)
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SDRAM Controller (107)
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984 IP
101
11.0
10.67Gbps LPDDR5/5X PHY & Controller
High performance, low power and area efficient memory interface solutions conforming to LPDDR5/5X (JESD209-5C) JEDEC standard. Extra RAS add-on featu...
102
11.0
HBM3 Controller IP
SmartDV's HBM3 Controller IP is a fully featured High Bandwidth Memory controller solution purpose-built for SoC designs requiring the highest availab...
103
11.0
HBM3 PHY & Controller
SkyeChip’s High Bandwidth Memory (HBM) IP consists of a PHY and memory controller optimized for TSMC N7, N12 and Samsung 4nm process to support the HB...
104
11.0
DDR5 Controller IP
SmartDV's DDR5 Controller IP is a silicon-proven, fully featured DDR5 DRAM memory controller solution purpose-built for SoC designs requiring next-gen...
105
11.0
DDR5/4 PHY & Controller
DDR5/4 PHY & Controller...
106
10.0
HBM3 Controller IP is optimized for power, latency, bandwidth, and area, supporting the JEDEC HBM3 standard
Synopsys HBM3 Controller IP is optimized for power, latency, bandwidth, and area, supporting the JEDEC HBM3 standard. The controller interoperates wit...
107
10.0
HBM3 PHY IP at 7nm
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
108
10.0
SD 3.0 / SDIO 3.0 Combo Device Controller
The SD / SDIO 3.0 Combo Device IP Core is a high performance controller capable of interfacing with memory cards and I/O applications such as WLAN, Bl...
109
10.0
SD 4.0 Device Controller
The SD 4.0 Device IP core is used to implement SD cards connected to a Host processor over standard SD bus. The flexible architecture of SD Device IP ...
110
10.0
SD 4.1 SDIO 4.1 Host Controller IP
The SD 4.1/SDIO 4.1 IP from Arasan Chip Systems is a highly integrated host controller IP solution that supports two key memory card I/O technologies:...
111
10.0
SD 6.0 UHS-III PHY
Silicon Library's world-first silicon proven UHS-III PHY is available in SMIC 65 now....
112
10.0
SD/eMMC in GF (12nm)
To address today’s content capacity and bandwidth requirements, JEDEC and SD Association continue to define new functionality and enhancements for emb...
113
10.0
SD/eMMC in TSMC (28nm, 16nm, 12nm, N7, N6)
To address today’s content capacity and bandwidth requirements, JEDEC and SD Association continue to define new functionality and enhancements for emb...
114
10.0
GDDR6 Memory Controller IP
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
115
10.0
GDDR6 PHY IP for 12nm
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
116
10.0
DDR and LPDDR 5/4/3/2 controllers for low power and high Reliability, Availability and Serviceability (RAS)
Synopsys offers a complete system-level memory interface IP portfolio for SoCs requiring an interface to one or a range of high-performance DDR5, DDR4...
117
10.0
DDR2/DDR3/DDR3L/LPDDR2 I/O Buffer - TSMC 40 CLN40LP
Analog Bits impedance programmable I/O buffer provides a high-speed physical interface solution to support the increasing bandwidths demanded by today...
118
10.0
DDR4 multiPHY in Samsung (14nm)
The Synopsys DDR4 multiPHY is a complete physical (PHY) layer IP interface solution for PC/consumer and mobile ASICs, ASSPs, system-on- chip (SoC), an...
119
10.0
DDR4 multiPHY in TSMC (28nm)
The Synopsys DDR4 multiPHY is a complete physical (PHY) layer IP interface solution for PC/consumer and mobile ASICs, ASSPs, system-on- chip (SoC), an...
120
10.0
DDR4 multiPHY in UMC (28nm)
The Synopsys DDR4 multiPHY is a complete physical (PHY) layer IP interface solution for PC/consumer and mobile ASICs, ASSPs, system-on- chip (SoC), an...
121
10.0
DDR4/3 PHY in Samsung (14nm, 11nm, 10nm, 8nm)
The Synopsys DDR4/3 PHY is a complete physical layer IP interface (PHY) solution for enterprise-class ASIC, ASSP, and system-on-chip (SoC) application...
122
10.0
DDR4/3 PHY in TSMC (12nm, 16nm, 7nm)
The Synopsys DDR4/3 PHY is a complete physical layer IP interface (PHY) solution for enterprise-class ASIC, ASSP, and system-on-chip (SoC) application...
123
10.0
DDR5 PHY in Samsung (SF4X)
The Synopsys DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-...
124
10.0
DDR5 Power Management IC
Power Management IC (PMIC) is designed for DDR5 RDIMM, DDR5 LRDIMM, DDR5 NVDIMM application. PMIC is used for switching and LDO regulators. PMIC-I3C I...
125
10.0
DDR5 Serial Presence Detect (SPD5) Hub Interface
The SPD5 Hub Function IP has been developed to interface I3C/I2C Host Bus and it allows an isolation of local devices like Temperature Sensor(TS), fro...
126
10.0
DDR5 Temperature Sensor - TS5111 and TS5110
he TS5111 and TS5110 device incorporate thermal sensing capability which is controlled and read over two wire bus. These device operate on I2C and I3C...
127
10.0
DDR5/4 PHY in GF (12nm)
The Synopsys DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-...
128
10.0
DDR5/4 PHY in Samsung (10nm, 8nm, 7nm)
The Synopsys DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-...
129
10.0
DDR5/4 PHY in TSMC (16nm, 12nm, N6, N7, N5)
The Synopsys DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-...
130
10.0
DDR5/4 PHY V2 in TSMC (N7, N6, N5)
The Synopsys DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-...
131
10.0
High performance and low latency hardware accelerated zram/zswap at unmatched power efficiency
The SuperRAM implements a hardware accelerator for zram compression and decompression. SuperRAM implements a ZeroPoint proprietary compression algorit...
132
10.0
eMMC 4.51 Device Controller
Arasan's eMMC 4.51 Memory controller is compliant with the latest MMC 4.51 specification released by JEDEC. The controller provides a peak bandwidth o...
133
10.0
Universal Multiport Memory Controller - LPDDR 3/2 Controller
Mobiveil's UMMC LPDDR3/2 Controller is a highly flexible and configurable design. It is targeted for high bandwidth access and low power consumption s...
134
10.0
Low-power SD/eMMC host controller IP provides advanced high-performance 32- and 64-bit AXI interface to the SoC
The Synopsys SD/eMMC Host Controller IP addresses the growing storage needs of mobile, consumer, IoT and automotive applications. The IP provides adva...
135
10.0
LPDDR5/4X PHY IP for TSMC
Lowest latency and highest data rates for data-intensive applications The LPDDR PHY IP is comprised of architectural improvements to its highly suc...
136
10.0
TSMC DDR3/4 & LPDDR3/4 Combo IP with AXI and DFI 4.0 Interface
This DDR3/4 and LPDDR3/4 IP combo solution integrates both controller and PHY, designed for TSMC 22nm process. It offers high-performance data rates u...
137
10.0
TSMC DDR3/4 & LPDDR3/4/4x Combo IP with Controller + PHY
This combo IP solution supports DDR3/DDR4 and LPDDR3/LPDDR4/LPDDR4x memory standards, designed for high performance and low power applications on TSMC...
138
8.0
TSMC CLN7FF HBM2E PHY IP
This datasheet describes GUC HBM (High Bandwidth Memory) PHY IP, which could be integrated with HBM memory controller to provide HBM functionality. Th...
139
6.0
SD Memory Card Host Controller
VinSDHC3_0 SD Host Controller Core controls data transfers between the SD Host System and the SD Memory Card sockets. It is compliant with the standar...
140
6.0
ONFI : Open NAND Flash Interface Host Controller
NAND Flash Interface controller that provides the means for a system to be designed that supports a range of NAND Flash devices without direct design ...
141
6.0
LPDDR4/DDR4/DDR3 PHY - TSMC 22nmULL
SP-LPD4/D43_PHY16BIT-T22ULL is designed for DRAM controller to connect to the LPDDR4/DDR4/3 DRAM memory device. It contains a DDR PHY Control Unit(DPC...
142
5.0
GDDR7 Memory PHY for GLOBALFOUNDRIES at 16Gbps
High performance for graphics, AI, and automotive products The Cadence IP solution for GDDR7 consists of high-performance hardened PHY, serving hig...
143
5.0
DDR3/4 and LPDDR2/3/4/4x Combo PHY&MAC
With sophisticated architecture and advanced technology, this DDR3/4 and LPDDR2/3/4/4x IP combo solution with high performance and low power. In 12~28...
144
5.0
DDR4/LPDDR4/LPDDR4X PHY
M31 LPDDR4X multi-PHY supports both LPDDR4 and LPDDR4X memory interfaces at speed up to 4267Mbps, making it an ideal solution for ASICS, ASSPs, SOC an...
145
5.0
AGILEX 7 R-Tile NVME HOST IP
Gen5 NVMe Host IP on AGILEX7 R-Tile It enables random access, sequential access, Read/Write access and multi-user access. To show these features, s...
146
5.0
Xilinx UltraScale Plus NVME Hhost IP
The LDS NVME HOST ZUP IP is one of the most flexible NVME HOST IP in the market. It has been done for beginners and expert in NVMe to drive NVMe PC...
147
5.0
Kintex Ultra Scale Plus NVMe Host IP
The LDS NVME HOST IP has been done for beginners and expert in NVMe to drive NVMe PCIe SSD. The LDS NVME HOST IP provides two interfaces : * On...
148
5.0
eMMC 5.1 HS400 PHY and I/O Pads in TSMC 16FF PLUS LL
Arasan provides a HS400 compatible PHY that customers can integrate with the HS400 I/O PADs. It is designed to optimize I/O performance with a core v...
149
5.0
eMMC 5.1 HS400 PHY and I/O Pads in TSMC 16FFC NS
Arasan provides a HS400 compatible PHY that customers can integrate with the HS400 I/O PADs. It is designed to optimize I/O performance with a core v...
150
5.0
eMMC 5.1 HS400 PHY and I/O Pads in TSMC 28HPC-NS
Arasan provides a HS400 compatible PHY that customers can integrate with the HS400 I/O PADs. It is designed to optimize I/O performance with a core v...
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