Design & Reuse
arrow AES Encryption Core (100)
arrow Cryptography (185)
arrow Data Integrity - Error Correction (18)
arrow Embedded Security Modules (26)
arrow Hardware Accelerator (42)
arrow MACsec, IPsec (32)
arrow Post-Quantum Solutions (36)
arrow PUF Based (20)
arrow Random Number Generator (RNG) (16)
arrow Root of Trust (18)
arrow Security Platform (38)
arrow Sensors & Monitors (9)
540 IP
201
4.0
AES-CTR Encryption Core
The IntelliProp IPC-BL204A-ZM is an AES-CTR (Counter Mode) Encryption Core supporting 128 or 256 bit encryption. The IPC-BL204A-ZM provides encryption...
202
4.0
AES-GCM Encryption Core
The IntelliProp IPC-BL193A-ZM is an AES-GCM (Galois Counter Mode) Encryption Core supporting 128 or 256 bit encryption. The IPC-BL193A-ZM provides enc...
203
4.0
SHA 256-bit hash generator
An n-bit hash is a map from arbitrary length messages to n-bit hash values. An n-bit cryptographic hash is an n-bit hash which is one-way and collisio...
204
4.0
SHA3 core for accelerating NIST FIPS 202 Secure Hash Algorithm
eSi-SHA3 is area-efficient hardware accelerator core for the SHA3 and SHAKE cryptographic hashing algorithms compliant with the NIST FIPS 202 standar...
205
4.0
High Throughput Additive White Gaussian Noise Generator
A configurable AWGN generator that can be used as emulator of a noisy transmission channel and can support very high throughput rates up to 10 Gbps....
206
4.0
NIST FIPS-197 Compliant High Throughput Rate AES IP Core
ntAES128 core implements the NIST FIPS-197 Advanced Encryption Standard and can be programmed to either encrypt or decrypt 128-bit blocks of data usin...
207
4.0
NIST FIPS-197 Compliant Ultra-Low Power AES IP Core
ntAES8 core implements NIST FIPS-197 Advanced Encryption Standard. ntAES8 core can be programmed to encrypt or decrypt 128-bit blocks of data using a ...
208
4.0
PKCS IP
The PKCS IP is specifically designed for RSA Laboratories' Public-Key Cryptography Standards (PKCS) series, specifically PKCS #5 v2.0. Also used for E...
209
4.0
Embedded Hardware Security Module (EVITA-Full Compliant)
PUFhsm is an embedded Hardware Security Module solution for automotive chips and general advanced applications. It is the latest offering from PUFsecu...
210
4.0
XTS mode AES Processor
The ntAES_XTS IP Core is fully compliant with AES-XTS algorithm standardized at NIST SP800-38E and IEEE 1619-2007 recommendations targeting disk encry...
211
3.0
802.11i CCM (CTR+CBC) AES Core for WiFi WLAN
Implementation of the new WLAN security standard 802.11i requires the NIST standard AES cipher in CTR and CBC modes (a.k.a. CCM) for encryption and me...
212
3.0
802.11i CCMP/TKIP IP Core
Implementation of the WLAN security standard (802.11i) requires the NIST standard AES cipher in CTR and CBC modes (a.k.a. CCM) for encryption and mess...
213
3.0
802.15.3 CCM AES Core
Implementation of the new WPAN security standard (802.15.3) requires the NIST standard AES cipher in CTR and CBC modes (a.k.a. CCM) for encryption and...
214
3.0
P1619/802.1ae (MACSec) GCM/XEX/XTS-AES Core
General Description LAN security standard IEEE 802.1ae (MACSec) uses AES cipher in the GCM mode, while the disk/tape encryption standard IEEE P1619 us...
215
3.0
Kasumi Encryption Core
The KSM1 core implements Kasumi encryption in compliance with the ETSI SAGE specification. It processes 64-bit blocks using 128-bit key. Basic core is...
216
3.0
MBOA MAC AES Core
Implementation of the new WPAN security standard for MBOA MAC requires the NIST standard AES cipher in CTR and CBC modes (a.k.a. CCM) for encryption ...
217
3.0
RC4 Keystream Generator
The RC4 core implements the RC4 stream cipher in compliance with the ARC4 specification. It produces the keystream that consists of 8-bit words using ...
218
3.0
Scalable RSA and Elliptic Curve Accelerator
Rivest-Shamir-Adelman (RSA) is a public-key cryptographic technology that uses the mathematics of so called “finite field exponentiation”. The operati...
219
3.0
HDCP 2.0 Encryption Suite
HDCP Suite consists of hardware and software components implementing the HDCP 2.0 protocol. The hardware components are fully synchronous and availab...
220
3.0
3DES Crypto Engine
The DES/3DES crypto engine offers a hardware implementation of the Data Encryption Standard (DES) according to Federal Information Processing Standard...
221
3.0
Advanced Encryption Standard (AES) core
The AES / Rijndael core can handle input block sizes of 128, 192 or 256 bit. The Decoder needs the key and the cipher text as input. The start_de sign...
222
3.0
IEEE 802.11 WAPI Encryption Core
Implementation of the new Chinese security standard (WAPI) requires running the SMS4 cipher in the WPI mode for encryption and message authentication....
223
3.0
IEEE 802.15.4 (ZigBee) CCM* AES Cores
IEEE 802.15.4 is the low-power wireless standard that is used by ZigBee Alliance as a base of its ZigBee™ specification. The security design of IEEE 8...
224
3.0
IEEE 802.16e (WiMAX) AES Core
Implementation of the new WLAN security standard (802.16e) requires the NIST standard AES cipher in CTR and CBC modes (a.k.a. CCM) for encryption and ...
225
3.0
IEEE 802.1ae (MACsec) 100G Security Processor with Avalon-ST Interface
Implementation of the new LAN security standard IEEE 802.1ae (MACsec) requires the NIST standard AES cipher in the GCM mode for encryption and message...
226
3.0
IEEE 802.1ae (MACsec) Security Processor
Implementation of the new LAN security standard IEEE 802.1ae (MACsec) requires the NIST standard AES cipher in the GCM mode for encryption and message...
227
3.0
Generic CCM AES Core
The CCM1 cores are tuned for mid-performance generic AES-CCM applications per NIST SP 800-38C. Specific protocol implementations are available in inte...
228
3.0
Generic CCM AES Core with CMAC Option
The CCM2 cores are tuned for mid-performance generic AES-CCM applications per NIST SP 800-38C. CCM2 core uses flow-trough design with dedicated input...
229
3.0
Generic Polar FEC Codec
Creonic has flexible Polar decoder architecture to fulfil different customer requirements. The IP core has been demonstrated on internal conferenc...
230
3.0
Generic Polar FEC Codec
Creonic has flexible Polar decoder architecture to fulfil different customer requirements. The IP core has been demonstrated on internal conferenc...
231
3.0
SHA1 core
The eSi-SHA1 core is an easy to use SHA1 hash accelerator peripheral. SHA1 is a cryptographic hash function designed by the United States National Sec...
232
3.0
SHA1, SHA2 Cryptographic Hash Cores
The SHA cores provide implementation of cryptographic hashes SHA-1 (core SHA1), SHA-2 (cores SHA2-256 and SHA2-512). The cores utilize “flow-through”...
233
3.0
ChaCha20 stream cipher core
The eSi-CHACHA20 core is an easy to use CHACHA20 stream cipher hardware accelerator that is compliant with the IETF RFC7539 standard. ChaCha20, alo...
234
3.0
High Throughput AES
This is a pipelined high throughput AES core capable of starting a new encryption every clock cycle. It is intended for both ASIC and FPGA target tec...
235
3.0
High-Performance Lossless Compression/Encryption Combo Core
Lossless data compression is a class of data compression algorithms that allows the exact original data to be reconstructed from the compressed data. ...
236
3.0
NIST AES Key Wrap/Unwrap Core
AKW1 implements the NIST standard AES key wrap and unwrap. Core contains the base AES core AES1 and is available for immediate licensing. The design ...
237
3.0
Elliptic Curve Point Multiply and Verify Core
Elliptic Curve Cryptography (ECC) is a public-key cryptographic technology that uses the mathematics of so called “elliptic curves” and it is a part o...
238
3.0
Ultra-Compact 3GPP Cipher Core
The ZUC1 core implements ZUC stream cipher in compliance with the 3GPP Confidentiality and Integrity Algorithms 128-EEA3 & 128-EIA3 version 1.6. It pr...
239
3.0
Ultra-Compact Advanced Encryption Standard (AES, FIPS-197) Core
The AES core implements Rijndael cipher encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit data bloc...
240
3.0
Ultra-Compact Data Encryption Standard (DES/3DES) Core
The DES1 ASIC/FPGA core is an implementation of the DES and triple DES encryption and decryption in compliance with the NIST Data Encryption Standard....
241
3.0
SNOW 3G Encryption Core
The SNOW3G1 core implements SNOW 3G stream cipher in compliance with the ETSI SAGE specification version 1.1. It produces the keystream that consists ...
242
3.0
Poly1305 core
The eSi-POLY1305 core is an easy to use POLY1305 accelerator peripheral that is fully compliant with the RFC7539 IETF standard. Poly1305, along wi...
243
3.0
Combined ChaCha20 and Poly1305 core
The eSi-CHACHA20-POLY1305 core is an easy to use APB hardware accelerator peripheral that is fully compliant with the IETF RFC7539 standard Poly1...
244
3.0
Configurable AES Core
eSi-AES is a range of sophisticated AES cores for use in ASIC or FPGA technologies. They can be configured to customer the requirements to enable a...
245
3.0
Upgraded PUF-based Crypto Coprocessor (Compliant with TLS 1.3 / FIPS 186-5)
PUFcc Series Crypto Coprocessor IP presents its uniqueness in the combination of a PUF-based hardware root of trust with a full suite of cryptographic...
246
3.0
True Random and Pseudorandom Number Generator
The true random generator core implements true random number generation. The core passes the American NIST Special Publication 800-22 and Diehard Rand...
247
3.0
LRW-AES Core
Implementation of the older drafts standard IEEE P1619 required the NIST standard AES cipher in the LRW mode for encryption (AES-LRW). Note that the n...
248
3.0
LRW-AES Core
Implementation of the new encrypted shared storage media standard IEEE P1619 with AES cipher in the LRW mode....
249
3.0
LRW-AES Core
LRW3 implements the NIST standard AES cipher in the LRW mode for encryption and decryption. The LRW3 family of cores covers a wide range of area / thr...
250
3.0
Cryptographically Secure Pseudo Random number Generator IP Core
The PRNG1 core implements a cryptographically secure pseudo-random number generator per NIST publication SP800-90. Basic core is small (6,500 gates)...