Security IP Core

The AES / Rijndael core can handle input block sizes of 128, 192 or 256 bit. The Decoder needs the key and the cipher text as input. The start_de sign...

252

3.0

IEEE 802.11 WAPI Encryption Core

Implementation of the new Chinese security standard (WAPI) requires running the SMS4 cipher in the WPI mode for encryption and message authentication....

253

3.0

IEEE 802.15.4 (ZigBee) CCM* AES Cores

IEEE 802.15.4 is the low-power wireless standard that is used by ZigBee Alliance as a base of its ZigBee™ specification. The security design of IEEE 8...

254

3.0

IEEE 802.16e (WiMAX) AES Core

Implementation of the new WLAN security standard (802.16e) requires the NIST standard AES cipher in CTR and CBC modes (a.k.a. CCM) for encryption and ...

255

3.0

IEEE 802.1ae (MACsec) 100G Security Processor with Avalon-ST Interface

Implementation of the new LAN security standard IEEE 802.1ae (MACsec) requires the NIST standard AES cipher in the GCM mode for encryption and message...

256

3.0

IEEE 802.1ae (MACsec) Security Processor

Implementation of the new LAN security standard IEEE 802.1ae (MACsec) requires the NIST standard AES cipher in the GCM mode for encryption and message...

257

3.0

Generic CCM AES Core

The CCM1 cores are tuned for mid-performance generic AES-CCM applications per NIST SP 800-38C. Specific protocol implementations are available in inte...

258

3.0

Generic CCM AES Core with CMAC Option

The CCM2 cores are tuned for mid-performance generic AES-CCM applications per NIST SP 800-38C. CCM2 core uses flow-trough design with dedicated input...

259

3.0

Generic Polar FEC Codec

Creonic has flexible Polar decoder architecture to fulfil different customer requirements. The IP core has been demonstrated on internal conferences...

260

3.0

SHA1 core

The eSi-SHA1 core is an easy to use SHA1 hash accelerator peripheral. SHA1 is a cryptographic hash function designed by the United States National Sec...

261

3.0

SHA1, SHA2 Cryptographic Hash Cores

The SHA cores provide implementation of cryptographic hashes SHA-1 (core SHA1), SHA-2 (cores SHA2-256 and SHA2-512). The cores utilize “flow-through”...

262

3.0

High Throughput AES

This is a pipelined high throughput AES core capable of starting a new encryption every clock cycle. It is intended for both ASIC and FPGA target tec...

263

3.0

High-Performance Lossless Compression/Encryption Combo Core

Lossless data compression is a class of data compression algorithms that allows the exact original data to be reconstructed from the compressed data. ...

264

3.0

NIST AES Key Wrap/Unwrap Core

AKW1 implements the NIST standard AES key wrap and unwrap. Core contains the base AES core AES1 and is available for immediate licensing. The design ...

265

3.0

Elliptic Curve Point Multiply and Verify Core

Elliptic Curve Cryptography (ECC) is a public-key cryptographic technology that uses the mathematics of so called “elliptic curves” and it is a part o...

266

3.0

Ultra-Compact 3GPP Cipher Core

The ZUC1 core implements ZUC stream cipher in compliance with the 3GPP Confidentiality and Integrity Algorithms 128-EEA3 & 128-EIA3 version 1.6. It pr...

267

3.0

Ultra-Compact Advanced Encryption Standard (AES, FIPS-197) Core

The AES core implements Rijndael cipher encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit data bloc...

268

3.0

Ultra-Compact Data Encryption Standard (DES/3DES) Core

The DES1 ASIC/FPGA core is an implementation of the DES and triple DES encryption and decryption in compliance with the NIST Data Encryption Standard....

269

3.0

SNOW 3G Encryption Core

The SNOW3G1 core implements SNOW 3G stream cipher in compliance with the ETSI SAGE specification version 1.1. It produces the keystream that consists ...

270

3.0

True Random and Pseudorandom Number Generator

The true random generator core implements true random number generation. The core passes the American NIST Special Publication 800-22 and Diehard Rand...

271

3.0

LRW-AES Core

Implementation of the older drafts standard IEEE P1619 required the NIST standard AES cipher in the LRW mode for encryption (AES-LRW). Note that the n...

272

3.0

LRW-AES Core

Implementation of the new encrypted shared storage media standard IEEE P1619 with AES cipher in the LRW mode....

273

3.0

LRW-AES Core

LRW3 implements the NIST standard AES cipher in the LRW mode for encryption and decryption. The LRW3 family of cores covers a wide range of area / thr...

274

3.0

Cryptographically Secure Pseudo Random number Generator IP Core

The PRNG1 core implements a cryptographically secure pseudo-random number generator per NIST publication SP800-90. Basic core is small (6,500 gates)...

275

3.0

RSA Public Key Exponentiation Accelerator

Rivest-Shamir-Adelman (RSA) is a public-key cryptographic technology that uses the mathematics of so called “finite field exponentiation”. The opera...

276

3.0

Pseudorandom Number Generator (PRNG) - Balanced variant

The PRNG IP core establishes a benchmark for hardware-based security in cryptographic systems by generating high-quality pseudorandom numbers. It deli...

277

3.0

Pseudorandom Number Generator (PRNG) - High-speed variant

The PRNG IP core establishes a benchmark for hardware-based security in cryptographic systems by generating high-quality pseudorandom numbers. It deli...

278

3.0

SSL/TLS Processor IP Core with an AXI Bus Interface

The SSL1 core implements SSL and/or TLS frameworks with a configurable variety of cipher suites. SSL1-AXI has a “lookaside” interface to the rest of...

279

3.0

XTS-AES IEEE P1619 Core Families

XTS2 and XTS3 (formerly known as XEX2 and XEX3) implement the NIST standard AES cipher in the XEX/XTS mode for encryption and decryption. The XTS3 fa...

280

2.0

GCM-AES Authenticated Encryption & Decryption

The AES-GCM128 core from Alma Technologies implements the GCM-AES authenticated encryption and decryption, as specified in the NIST SP800-38D recommen...

281

2.0

AES Encryption & Decryption with Programmable Block-Cipher Mode

The AES-P core from Alma Technologies implements the FIPS-197 Advanced Encryption Standard. It can be programmed to encrypt or decrypt 128-bit blocks ...

282

2.0

AES IP Core

Encryption and Decryption are fed with an input of 128 bits length and an initial key of one of the supported key lengths (128, 192 and 256). The AES...

283

2.0

SHA512 & SHA384 core

The eSi-SHA512 core is an easy to use SHA hash accelerator peripheral for both SHA512 and SHA384. This is a cryptographic hash function designed by t...

284

2.0

Clock Attack Monitor GlobalFoundries

The agileCAM is a Ring Oscillator (RO) based clock attack monitor designed to detect clock attacks due to violation of the set-up time requirements of...

285

2.0

Clock Attack Monitor Intel

The agileCAM is a Ring Oscillator (RO) based clock attack monitor designed to detect clock attacks due to violation of the set-up time requirements of...

286

2.0

Clock Attack Monitor Samsung

The agileCAM is a Ring Oscillator (RO) based clock attack monitor designed to detect clock attacks due to violation of the set-up time requirements of...

287

2.0

Clock Attack Monitor SMIC

The agileCAM is a Ring Oscillator (RO) based clock attack monitor designed to detect clock attacks due to violation of the set-up time requirements of...

288

2.0

Clock Attack Monitor TSMC

The agileCAM is a Ring Oscillator (RO) based clock attack monitor designed to detect clock attacks due to violation of the set-up time requirements of...

289

2.0

Clock Attack Monitor UMC

The agileCAM is a Ring Oscillator (RO) based clock attack monitor designed to detect clock attacks due to violation of the set-up time requirements of...

290

2.0

Voltage Glitch Sensor GlobalFoundries