Design & Reuse
506 IP
251
3.0
NIST AES Key Wrap/Unwrap Core
AKW1 implements the NIST standard AES key wrap and unwrap. Core contains the base AES core AES1 and is available for immediate licensing. The design ...
252
3.0
Elliptic Curve Point Multiply and Verify Core
Elliptic Curve Cryptography (ECC) is a public-key cryptographic technology that uses the mathematics of so called “elliptic curves” and it is a part o...
253
3.0
Ultra-Compact 3GPP Cipher Core
The ZUC1 core implements ZUC stream cipher in compliance with the 3GPP Confidentiality and Integrity Algorithms 128-EEA3 & 128-EIA3 version 1.6. It pr...
254
3.0
Ultra-Compact Advanced Encryption Standard (AES, FIPS-197) Core
The AES core implements Rijndael cipher encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit data bloc...
255
3.0
Ultra-Compact Data Encryption Standard (DES/3DES) Core
The DES1 ASIC/FPGA core is an implementation of the DES and triple DES encryption and decryption in compliance with the NIST Data Encryption Standard....
256
3.0
SNOW 3G Encryption Core
The SNOW3G1 core implements SNOW 3G stream cipher in compliance with the ETSI SAGE specification version 1.1. It produces the keystream that consists ...
257
3.0
Poly1305 core
The eSi-POLY1305 core is an easy to use POLY1305 accelerator peripheral that is fully compliant with the RFC7539 IETF standard. Poly1305, along wi...
258
3.0
Combined ChaCha20 and Poly1305 core
The eSi-CHACHA20-POLY1305 core is an easy to use APB hardware accelerator peripheral that is fully compliant with the IETF RFC7539 standard Poly1...
259
3.0
Configurable AES Core
eSi-AES is a range of sophisticated AES cores for use in ASIC or FPGA technologies. They can be configured to customer the requirements to enable a...
260
3.0
True Random and Pseudorandom Number Generator
The true random generator core implements true random number generation. The core passes the American NIST Special Publication 800-22 and Diehard Rand...
261
3.0
LRW-AES Core
Implementation of the older drafts standard IEEE P1619 required the NIST standard AES cipher in the LRW mode for encryption (AES-LRW). Note that the n...
262
3.0
LRW-AES Core
Implementation of the new encrypted shared storage media standard IEEE P1619 with AES cipher in the LRW mode....
263
3.0
LRW-AES Core
LRW3 implements the NIST standard AES cipher in the LRW mode for encryption and decryption. The LRW3 family of cores covers a wide range of area / thr...
264
3.0
Cryptographically Secure Pseudo Random number Generator IP Core
The PRNG1 core implements a cryptographically secure pseudo-random number generator per NIST publication SP800-90. Basic core is small (6,500 gates)...
265
3.0
RSA Public Key Exponentiation Accelerator
Rivest-Shamir-Adelman (RSA) is a public-key cryptographic technology that uses the mathematics of so called “finite field exponentiation”. The opera...
266
3.0
Pseudorandom Number Generator (PRNG) - Balanced variant
The PRNG IP core establishes a benchmark for hardware-based security in cryptographic systems by generating high-quality pseudorandom numbers. It deli...
267
3.0
Pseudorandom Number Generator (PRNG) - High-speed variant
The PRNG IP core establishes a benchmark for hardware-based security in cryptographic systems by generating high-quality pseudorandom numbers. It deli...
268
3.0
SSL/TLS Processor IP Core with an AXI Bus Interface
The SSL1 core implements SSL and/or TLS frameworks with a configurable variety of cipher suites. SSL1-AXI has a “lookaside” interface to the rest of...
269
3.0
XTS-AES IEEE P1619 Core Families
XTS2 and XTS3 (formerly known as XEX2 and XEX3) implement the NIST standard AES cipher in the XEX/XTS mode for encryption and decryption. The XTS3 fa...
270
2.0
GCM-AES Authenticated Encryption & Decryption
The AES-GCM128 core from Alma Technologies implements the GCM-AES authenticated encryption and decryption, as specified in the NIST SP800-38D recommen...
271
2.0
AES Encryption & Decryption with Programmable Block-Cipher Mode
The AES-P core from Alma Technologies implements the FIPS-197 Advanced Encryption Standard. It can be programmed to encrypt or decrypt 128-bit blocks ...
272
2.0
AES IP Core
Encryption and Decryption are fed with an input of 128 bits length and an initial key of one of the supported key lengths (128, 192 and 256). The AES...
273
2.0
SHA512 & SHA384 core
The eSi-SHA512 core is an easy to use SHA hash accelerator peripheral for both SHA512 and SHA384. This is a cryptographic hash function designed by t...
274
2.0
Voltage Glitch Detector for Anti-Tamper Solution
The agileVGLITCH voltage monitor provides security and protection against voltage side-channel attacks (SCA) and tampering such as supply voltage chan...
275
1.0
AES Encryption & Decryption with Fixed Block-Cipher Mode
The AES-C core from Alma Technologies implements the FIPS-197 Advanced Encryption Standard. It can be programmed to encrypt or decrypt 128-bit blocks ...
276
1.0
DES/TDES core
The eSi-DES block performs encryption and decryption of 64-bit words using the DES (Data Encryption Standard) and TDEA (Triple DES Encryption Algorith...
277
1.0
SHA256 & SHA224 core
The eSi-SHA256 core is an easy to use SHA hash accelerator peripheral for both SHA256 and SHA224. This is a cryptographic hash function designed by t...
278
1.0
enhanced AES
FIPS-197 Compliant. Encrypt and decrypt modules with 128, 192 and 256 bit keys. Various versions are available, from small area to high performance, u...
279
1.0
Enhanced AES with CCM mode
FIPS-197 Compliant. Encrypt and decrypt modules with 128, 192 and 256 bit keys. Various versions are available, from small area to high performance, u...
280
1.0
Power and area optimised Bitcoin miner engine
The eSi-BTC core is a Bitcoin miner engine that perform double SHA256 Hash. It is design to deliver best in class silicon area and power for the next...
281
1.0
GPON FEC 2.5 Gbps
This high performance core is a full featured Forward Error Correction encoder and decoder, specially designed for high speed optical networks or any ...
282
1.0
nQrux® Confidential Computing Engine (CCE)
nQrux® Confidential Computing Engine (CCE) offers customisable solutions protecting data, code execution, and AI (Artificial Intelligence) models in d...
283
1.0
RSA public key cryptography with APB interface
The standard RSA module is available as an APB peripheral, where it seamlessly integrates with EnSilica's cryptography library. The peripheral can ...
284
1.0
PUF Security
A physical unclonable function, or PUF, is a "digital fingerprint" that serves as a unique identity for a semiconductor device such as a microprocesso...
285
1.0
PUF-based Hardware Root of Trust
PUFrt is a Hardware Root of Trust (HRoT) offering the essential features necessary for establishing a trusted foundation from which all security opera...
286
1.0
Cypher Processor IP
Vivante’s CYP800 (CYPher) Processor IP encryption and decryption fabric provides a unified data encryption and decryption infrastructure for the SoC....
287
0.0
G.hn AES-CCM Core
Implementation of the new ITU G.9961 standard for home networking requires the NIST standard AES cipher in CTR and CBC modes (a.k.a. CCM) for encrypti...
288
0.0
400G AES Encryption Core
The 400G AES Encryption Core is a high performance and yet low footprint AES engine for 400G/s application. Typical applications are providing bulk en...
289
0.0
800G Channelized Ethernet MACsec IP
The Rianta Solutions MACsec IP cores are best-in-class, fully-featured 1G to 800G channelized MACsec streaming processor cores supporting both LAN and...
290
0.0
10G/25G/40G/50G AES Encryption Core
The 10G/25G/40G/50G AES Encryption Core is a high performance and yet low footprint AES engine for 10G/s - 50G/s application. Typical applications are...
291
0.0
P1619/802.1ae (MACSec) GCM/XEX/XTS-AES Core
General Description LAN security standard IEEE 802.1ae (MACSec) uses AES cipher in the GCM mode, while the disk/tape encryption standard IEEE P1619 us...
292
0.0
13 Different Cryptographic Hash Functions Core
These are 13 different cryptographic hash function originally submitted to NIST hash function competition which made upto round 2. All of these cores ...
293
0.0
MACsec - Balanced - Security Protocol
MACsec is a point-to-point protocol located on layer two (Data Link) of the OSI model. Xiphera's comprehensive MACsec solution portfolio safeguards th...
294
0.0
MACsec - High-speed - Security Protocol
MACsec is a point-to-point protocol located on layer two (Data Link) of the OSI model. Xiphera's comprehensive MACsec solution portfolio safeguards th...
295
0.0
MACsec software toolkit
INSIDE Secure provides a complete MACsec solution to secure Ethernet through its MACsec software toolkit and family of SafeXcel Hardware IP MACsec Sec...
296
0.0
RADIX-M Emulation Based Security Verification
Radix-M provides SoC system level hardware security verification leveraging commercial emulators for firmware and hardware security validation. By run...
297
0.0
RADIX-S - Simulation Based Security Verification
Radix-S is used during design creation and verification to detect and remediate security issues in IP blocks and subsystems of an SoC. Its advanced i...
298
0.0
Walnut DSA (TM) Fast, Future-Proof Digital Signature Algorithm Designed for Low-Resource Devices
WalnutDSA™ is a fast, small footprint, future-proof, public-key digital signature solution for low-resource devices–running on 8-, 16-, an...
299
0.0
Camellia Crypto Accelerator
The Camellia Engine implements the Camellia crypto algorithm, as specified in “Specification of Camellia” and RFC3713. Designed for fast integration...
300
0.0
HASH Accelerator with SHA-3, SHA-2, SHA-1
The EIP-57 is the IP for accelerating the various secure hash integrity algorithms like MD5 (RFC1231), SHA-1 (FIPS-180-2), SHA-2 (FIPS-180-3/4) and SH...