801 0.118

Standard Cell (High Voltage) Library IP, 9 tracks, UMC 0.162um eHV process UMC 0.162um eHV 3.3V/8.25V/16.5V process Standard Cell Library....

802 0.118

Standard Cell (High Voltage) Library IP, UMC 0.13um HS/FSG process UMC 0.13um HS/FSG process 3.3V Device Core Cell Library for RTC/PMU usage....

803 0.118

Standard Cell (MiniLib) Library IP, 6 tracks, UMC 0.13um LL/FSG process UMC 0.13um LL/FSG Logic process Mini-Library+....

804 0.118

Standard Cell (MiniLib) Library IP, 7 tracks, UMC 0.18um G2 process UMC 0.18um GII Logic process high-density/Low Power Core Cell Library....

805 0.118

Standard Cell (MiniLib) Library IP, 7 tracks, UMC 0.18um LL process UMC 0.18um MM/RF process Mini Cell Library....

806 0.3729

Low Power/Ultra Low Power Via Programmable ROM Compiler with Row/Column Redundancy Option, supports process G/LP/LP_eDRAM/ULP/ULPEF Specialty Memory Solutions...

807 0.118

Standard Cell (MiniLib) Library IP, 7 tracks, UMC 0.18um LL process UMC 0.18um MM/RF process Mini Cell Library....

808 0.118

Standard Cell (MiniLib) Library IP, 6 tracks, UMC 0.11um eFlash/HS process UMC 0.11um eFlash/EE2PROM AL process Mini-Library+ (6-Track) Library....

809 0.118

Standard Cell (MiniLib) Library IP, HVT, 7 tracks, UMC 28nm HLP process UMC 28nm HLP/HVT Logic and Mixed-Mode process 7-Track Generic Core Cell Library....

810 0.118

Standard Cell (MiniLib) Library IP, HVT, 7 tracks, UMC 28nm HLP process UMC 28nm HLP/HVT Logic and Mixed-Mode process 7-Track Generic Core Cell Library with LPLUS (C38)....

811 0.118

Standard Cell (MiniLib) Library IP, LVT, 7 tracks, UMC 28nm HLP process UMC 28nm HLP/LVT Logic and Mixed-Mode process 7-Track Cell Library with LMINUS (C30 LVT)....

812 0.118

Standard Cell (MiniLib) Library IP, LVT, 7 tracks, UMC 28nm HLP process UMC 28nm HLP/LVT Logic and Mixed-Mode process 7-Track Generic Core Cell Library....

813 0.118

Standard Cell (MiniLib) Library IP, LVT, 7 tracks, UMC 28nm HLP process UMC 28nm HLP/LVT Logic and Mixed-Mode process 7-Track Generic Core Cell Library wtih LPLUS (C38)....

814 0.118

Standard Cell (MiniLib) Library IP, RVT, 7 tracks, UMC 28nm HLP process UMC 28nm HLP/RVT Logic and Mixed-Mode process 7-Track Cell Library with LMINUS (C30 RVT)....

815 0.118

Standard Cell (MiniLib) Library IP, RVT, 7 tracks, UMC 28nm HLP process UMC 28nm HLP/RVT Logic and Mixed-Mode process 7-Track Generic Core Cell Library....

816 0.118

Standard Cell (MiniLib) Library IP, RVT, 7 tracks, UMC 28nm HLP process UMC 28nm HLP/RVT Logic and Mixed-Mode process 7-Track Cell Library with LPLUS (C38 RVT)....

817 0.3729

Low Power/Ultra Low Power Ternary-CAM/Binary-CAM, supports process GP/LP/LPEF/ULP/ULPEF Specialty Memory Solutions...

818 0.118

Standard Cell (MiniLib) Library IP, HVT, 7 tracks, UMC 40nm LP process UMC 40nm LP/HVT Low-K Logic process 7-Track Generic Core Cell Library....

819 0.118

Standard Cell (MiniLib) Library IP, LVT, 7 tracks, UMC 40nm LP process UMC 40nm LP/LVT Low-K Logic process 7-Track Generic Core Cell Library....

820 0.118

Standard Cell (MiniLib) Library IP, RVT, 7 tracks, UMC 40nm LP process UMC 40nm LP/RVT Low-K Logic process 7-Track Generic Core Cell Library....

821 0.118

Standard Cell (MiniLib) Library IP, HVT, 7 tracks, UMC 55nm LP process UMC 55nm LP/HVT Low-K Logic process 7-Track Mini-Library....

822 0.118

Standard Cell (MiniLib) Library IP, LVT, 7 tracks, UMC 55nm LP process UMC 55nm LP/LVT Low-K Logic process 7-Track Generic Core Cell Library....

823 0.118

Standard Cell (MiniLib) Library IP, RVT, 7 tracks, UMC 55nm LP process UMC 55nm LP/RVT Low-K Logic process 7-Track Generic Core Cell Library....

824 0.118

Standard Cell (MiniLib) Library IP, HVT, 7 tracks, UMC 55nm SP process UMC 55nm SP/HVT Logic process 7-Track Mini Cell Library....

825 0.118

Standard Cell (MiniLib) Library IP, RVT, 7 tracks, UMC 55nm SP process UMC 55nm SP/RVT Logic process 7-Track Generic Core Cell Library....

826 0.118

Standard Cell (Ultra High Speed) Library IP, HVT, 12 tracks, UMC 55nm eHV process UMC 55nm HV/HVT Low-K Logic process high speed Standard Core Library....

827 0.118

Standard Cell (Ultra High Speed) Library IP, HVT, 12 tracks, UMC 55nm SP process UMC 55nm SP/HVT Low-K Logic process UHS Cell Library....

828 0.3729

Low Power/Ultra Low Power Dual Port SRAM Compiler with Row/Column Redundancy Option, supports process GP/LP/LPEF/ULP/ULPEF Memory Compilers...

829 0.118

Standard Cell (Ultra High Speed) Library IP, HVT, 12 tracks, UMC 55nm LP process UMC 55nm LP/HVT Low-K Logic process 12-Track Generic Core Cell Library....

830 0.118

Standard Cell PowerSlash(TM) Library IP, HVT, 12 tracks, UMC 55nm LP process UMC 55nm LP/HVT Low-K Logic process 12-Track Generic Core Cell Library....

831 0.118

Standard Cell (Ultra High Speed) Library IP, LVT, 12 tracks, UMC 55nm LP process UMC 55nm LP/LVT Low-K Logic process 12-Track Generic Core Cell Library....

832 0.118

Standard Cell (Ultra High Speed) Library IP, RVT, 12 tracks, UMC 55nm LP process UMC 55nm LP/RVT Low-K Logic process 12-Track Generic Core Cell Library....

833 0.118

Standard Cell PowerSlash(TM) Library IP, 8 tracks, UMC 0.11um eFlash/HS process UMC 0.11um eFlash/HS process 8-Track Generic Core Cell Library....

834 0.118

Standard Cell PowerSlash(TM) Library IP, 7 tracks, UMC 0.11um HS/FSG process UMC 0.11um HS/FSG Logic process high density POWERSLASH (POWERSLASH) Core Cell Library....

835 0.118

Standard Cell PowerSlash(TM) Library IP, UMC 0.11um LL/FSG process UMC 0.11um LL/FSG Logic process high density POWERSLASH Core Cell Library....

836 0.118

Standard Cell PowerSlash(TM) Library IP, 8 tracks, UMC 0.11um eFlash/LL process UMC 0.11um eFlash/LL process 8-Track Cell Library....

837 0.118

Standard Cell PowerSlash(TM) Library IP, UMC 0.13um SP/FSG process UMC 0.13um SP FSG Logic process high density POWERSLASH Core Cell Library....

838 0.118

Standard Cell PowerSlash(TM) Library IP, UMC 0.13um HS/FSG process UMC 0.13um HS/FSG process FSC0H_J POWERSLASHKit core Library....

839 0.3729

Low Power/Ultra Low Power Pseudo 2 Ports SRAM Compiler with Row/Column Redundancy Option, supports process GP/LP/LPEF/ULP/ULPEF Memory Compilers...

840 0.118

Standard Cell PowerSlash(TM) Library IP, UMC 0.13um LL/FSG process UMC 0.13um LL FSG Logic process high density POWERSLASH Core Cell Library....

841 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, 9 tracks, UMC 28nm HLP process UMC 28nm Logic and Mixed-Mode HLP/RVT process 9-Track POWERSLASH Cell Library (C35)....

842 0.118

Standard Cell PowerSlash(TM) Library IP, HVT, 7 tracks, UMC 28nm HLP process UMC 28nm HLP/HVT Logic and Mixed-Mode process 7-Track POWERSLASH Cell Library....

843 0.118

Standard Cell PowerSlash(TM) Library IP, LVT, 7 tracks, UMC 28nm HLP process UMC 28nm HLP/LVT Logic and Mixed-Mode process 7-Track POWERSLASH Cell Library....

844 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 28nm HLP process UMC 28nm HLP/RVT Logic and Mixed-Mode process 7-Track POWERSLASH Cell Library....

845 0.118

Standard Cell PowerSlash(TM) Library IP, HVT, 12 tracks, UMC 28nm HLP process UMC 28nm Logic and Mixed-Mode HLP/HVT process 12-Track POWERSLASH Cell Library (C35)....

846 0.118

Standard Cell PowerSlash(TM) Library IP, LVT, 12 tracks, UMC 28nm HLP process UMC 28nm Logic and Mixed-Mode HLP/LVT process 12-Track POWERSLASH Cell Library (C35)....

847 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, 12 tracks, UMC 28nm HLP process UMC 28nm Logic and Mixed-Mode HLP/RVT process 12-Track Standard POWERSLASH Core Cell Library (C35)....

848 0.118

Standard Cell PowerSlash(TM) Library IP, HVT, 9 tracks, UMC 40nm LP process UMC 40nm LP/HVT Logic process 9-Track Standard Cell Library (POWERSLASH Core)....

849 0.118

Standard Cell PowerSlash(TM) Library IP, LVT, 9 tracks, UMC 40nm LP process UMC 40nm LP/LVT Logic process 9-Track Standard Cell Library (POWERSLASH Core)....

850 0.3729

Low Power/Ultra Low Power MultiBank Single Port SRAM Compiler with Row/Column Redundancy Option, with Low Leak support, short and long channel, inputs isolation, dual-rails, register scan, supports process GP/LP/LPEF/ULP/ULPEF Memory Compilers...