101 10.0

Differential Output Buffer - TSMC 6FF Analog Bits’ Differential Output Driver macros provide a low noise, high performance differential output clock. The output driver design implements a ...

102 10.0

Differential Output Buffer - TSMC N5 Analog Bits’ Differential Output Driver macros provide a low noise, high performance differential output clock. The output driver design implements a ...

103 10.0

Differential Signal Receiver - TSMC 6FF Analog Bits Differential Signal Receiver macro is a receiver including on-chip termination, and addresses a large portfolio of applications. The Recei...

104 10.0

Differential Signal Receiver - TSMC N5 Analog Bits Differential Signal Receiver macro is a receiver including on-chip termination, and addresses a large portfolio of applications. The Recei...

105 10.0

Glitch Detector - TSMC N5 Analog Bits’ Glitch Detector macro comprehensively addresses typical SOC power supply and other voltage glitch monitoring needs in a fully integrated ...

106 5.0556

A TSMC 65nm Wirebond IO library with 1-3.3V GPIO, 3.3V pulse-width modulation cell, I2C & SVID open-drain, 3.3V & 5V analog and OTP program cell Key attributes of our TSMC 65nm IO library include dual independent IO supply rails (1.0V-3.3V & 3.3V) and power-on-control (POC) to place IOs in a lo...

107 5.0556

A 180nm Flip-Chip IO library with 1.2-1.8V GPIO, 1.8V & 5V analog/RF, 20-36V ultra-low leakage low-cap HV analog and OTP program cell This silicon proven Certus 180 IO library is specifically tailored to address gaps in the native foundry IO offerings for this node. It features a 1....

108 4.0556

A 65nm Wirebond IO library with 2.5V GPIO, LVDS TX & RX and 2.5V analog / RF Key attributes of the GlobalFoundries 65nm IO library are dual selectable drive strengths and independent input & output enable / disable. The GPIO ce...

109 3.0

Voltage Domain Interfacing Cells for use between power domains using core transistors. Level shifters are add-ons to Dolphin standard cell library solutions and voltage regulator solutions. LS-CDM are High-Low and Low-High Level Shifter...

110 4.0556

LVDS RX & TX IOs in multiple foundry technology Certus provides full LVDS RX & TX IOs in GlobalFoundries and other foundry technologies. The Certus LVDS solutions are ANSI/TIA/EIA-644-A compliant a...

111 4.0556

High-voltage solutions in baseline TSMC and GlobalFoundries technology Certus is pleased to offer High-voltage ESD solutions across multiple baseline technologies. Distinguishing Certus is our ability to provide high-vol...

112 11.0

NVM OTP NeoBit in SHARP (180nm) eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...

113 11.0

NVM OTP NeoBit in Samsung (130nm) eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...

114 11.0

NVM OTP NeoBit in NEXCHIP (150nm, 110nm) eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...

115 11.0

NVM OTP NeoBit in Maxchip (180nm, 160nm, 150nm, 110nm, 90nm, 80nm) eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...

116 11.0

NVM OTP NeoBit in MagnaChip (350nm, 180nm, 150nm, 130nm, 110nm) eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...

117 11.0

NVM OTP NeoBit in JSC (130nm) eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...

118 11.0

NVM OTP NeoBit in Huali (55nm) eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...

119 11.0

NVM OTP NeoBit in HJTC (180nm, 160nm, 110nm) eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...

120 20.0

NVM OTP in Dongbu (180nm, 150nm, 110nm) Synopsys Non-Volatile Memory (NVM) IP provides reprogrammable NVM supporting up to 1 million bits (1Mbit) configurations in standard CMOS and BCD proc...

121 2.0

Single Port SRAM compiler - Memory optimized for ultra high density and high speed - compiler range up to 64 k Single Port SRAM compiler - TSMC 130 nm BCD Plus - Memory optimized for ultra high density and high speed - compiler range up to 64 k...

122 11.0

NVM OTP NeoBit in GTA (150nm) eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...

123 11.0

NVM OTP NeoBit in Grace (180nm, 160nm, 130nm, 110nm) eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...

124 11.0

NVM OTP NeoBit in GLOBALFOUNDRIES (350nm, 250nm, 180nm, 160nm, 150nm, 130nm, 110nm, 65nm, 55nm) eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...

125 11.0

NVM OTP NeoBit in Fujitsu (180nm) eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...

126 11.0

NVM OTP NeoBit in DongbuAnam (180nm, 160nm, 130nm, 110nm) eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...

127 11.0

NVM OTP NeoBit in CSMC (350nm, 250nm, 180nm, 160nm) eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...

128 11.0

NVM OTP NeoBit in CANSEMI (180nm, 110nm) eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...

129 11.0

NVM OTP NeoBit in ASMC (350nm) eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...

130 0.0

3DIO PHY IP for TSMC N5 Synopsys 3DIO is a specialized IO for multi-die integration. It includes multiple IP offerings for system-on-chip (SoC) designers to implement tunable...

131 0.0

Four Channel (4CH) LVDS Receiver in TSMC 40LP The MXL-LVDS-4CH-RX-T-40LP is a high-performance 4-channel LVDS Receiver implemented using digital CMOS technology. Both the serial and parallel data ...

132 0.0

Single Port SRAM compiler - Memory optimized for ultra high density and high speed - compiler up to 64 k Foundry Sponsored - Single Port SRAM 2048X32 instance - TSMC 130 nm BCD Plus - Memory optimized for ultra high density and high speed...

133 0.0

TSMC embedded flash controller The eSi-TSMC-Flash IP core provides an AMBA 3 AHB-lite interface to TSMC's embedded flash macros....

134 20.0

LVDS IO handling data rate up to 50Mbps with maximum loading 60pF KA16UGLVDS01ST001 is a LVDS IO handling data rate up to 50Mbps with a maximum loading of 60pF. The differential voltage swing can be programmable from...

135 5.0

Inline CUP I/O The inline CUP I/O library provide 3.3V bi- directional I/O cells with pull -up, pull-down features, Schmitt trigger and a range of drive strengths....

136 0.0

3.125 Gbps DDR CML receiver 065TSMC_CML_01 core logic interface includes complementary output signal pins (OUTp, OUTn) for data transmission and enable pin EN_RX. PAD_INP and PAD...

137 0.0

3.125 Gbps DDR 1-channel CML transmitter 065TSMC_CML_02 core logic interface includes signal pins (INP1, INP2 and INN1, INN2) for data transmission, control pin EN_TX to configure transmitter...

138 0.0

Up to 1.25 Gbps DDR LVDS IPs library 130TSMC_LVDS_04 is a library including: • Transmitter LVDS driver (LVDS_TX); • Receiver LVDS driver (LVDS_RX); • Bandgap reference block (LVDS_BG)...

139 0.0

1 Gbps LVDS Transmitter The interface to the core logic includes signal pin (INP) to transmit data and control pin ( EN) to configure the state of the transmitter. There are ...

140 0.0

Rail to rail LVDS receiver 1 Gbps LVDS_RX is LVDS receiver with rail to rail input range. The interface to the core logic includes the output signal pin (OUTp) to receive data and the ...

141 0.0

1.2 Gbps LVDS transmitter/receiver The interface to the core logic in receiver mode includes the signal pins (out_p and out_n) to receive data and the control pins (en_rx, ten, t_cal ar...

142 0.0

2 Gbps Rail to Rail LVDS receiver 065TSMC_LVDS_10 is LVDS receiver with rail to rail input range. EN_T enables 100 Ohm internal resistor. The CAL_T adjusts 100 Ohm internal resistor, t...

143 0.0

Metal programmable ROM compiler - Non volitile memory optimized for low power - compiler range up to 256 k Metal programmable ROM compiler - TSMC 130 nm BCD Plus - Non volatile memory optimized for low power - compiler range up to 256 k...

144 0.0

500Mbps LVDS IP library 180TSMC_LVDS_10 is a library including: • Transmitter LVDS driver (TX_LVDS); • Receiver LVDS driver (RX_LVDS); • Transceiver LVDS driver (R...

145 0.0

1Kbyte EEPROM (NTLab) The block is a nonvolatile electrically erasable programmable read-only memory (EEPROM) with volume 1Kbyte (16(bit per word) x 8(words per page) x 64(...

146 0.0

200 Mbps LVDS IP library 055TSMC_LVDS_03 is a library including: • Transmitter LVDS driver (TX_LVDS); • Receiver LVDS driver (RX_LVDS); • Reference current/voltage genera...

147 1.0

1Kbyte Embedded EEPROM with configuration 64p8w16bit The block is a nonvolatile electrically erasable programmable read-only memory (EEPROM) with volume 1 Kbyte (16(bit per word) x 8(words per page) x 64...

148 1.0

4 Gbps DDR CML receiver and transmitter 055TSMC_CML_01 is a library including: - CML receiver (CML_RX); - CML transmitter (CML_TX). The CML_RX block is intended to receive a CML signal a...

149 1.0

SMIC18 General process, Multi-Voltage IO with high voltage voltence SMIC18 General process, Multi-Voltage IO, driver current: 2mA~16mA when 3.3v IO supply...

150 1.0

VeriSilicon GSMC 0.18um 1.8v/3v/5v Mult IO for SIMcard VeriSilicon GSMC 0.18um 1.8V/3.3V Multiple I/O Cell (08) Library developed by VeriSilicon is optimized for Grace Semiconductor Manufacturing Corporati...