101 7.0

PowerMiser Ultra Low Power Embedded SRAM SE 28FDS PowerMiser(TM) delivers best-in-class static and dynamic power performance. Its patented “Bit Line Voltage Control” techniques eliminate performance c...

102 4.0

Cryogenic SP SRAM qualified down to 4K operating temperature Our range of CryoCMOS IP is suitable for operation at the extremely low temperature required for Quantum Computing (QC) applications. This CryoIP ™ fa...

103 6.0

MultiPort Low Voltage Register File MiniMiser™ is a tuneable multi-port register file architecture that can support both low power and high-performance applications. Its unique implement...

104 0.0

7 track Extra Low Consumption standard cell library with Dual voltage capability (1.8 V / 1.1 V) TSMC 180 G, SESAME HD DV optimized for high density and low power, with characterizations taking into account physical phenomena linked to low voltage...

105 0.0

In-memory computing CompuRAM™ provides In Memory Computing (IMC) that will enable solutions for computing at the Edge to be more power efficient. At present, sensor data ...

106 0.0

Four Channel LVDS Serializer in TSMC 130nm The MXL-SR-LVDS-4CH7-130 is a high performance 4-channel LVDS Serializer implemented using digital CMOS technology. Both the serial and parallel data ...

107 0.0

Four Channel (4CH) LVDS Serializer in Samsung 28FDSOI The 28FDSOI-LVDS-4CH-TX-1250-PLL is a high performance 4-channel LVDS Serializer implemented using digital CMOS technology. Both the serial and parall...

108 0.0

Eight Channel (8CH) LVDS Serializer in Samsung 28FDSOI The 28FDSOI-LVDS-1250-8CH-TX-PLL is a high performance 8-channel LVDS Serializer implemented using digital CMOS technology. Both the serial and parall...

109 12.0

180nm MTP Non Volatile Memory for Standard CMOS Logic Process NSCore's TwinBit(TM) is the only embedded CMOS, multi-time programmable (MTP), non-volatile RAM IP of its kind, utilizing the 'hot carrier effect' to ...

110 12.0

FTP Non Volatile Memory for Standard TSMC 40nm ULP Process NSCore's TwinBit(TM)FTP is the only embedded CMOS, few-time programmable (FTP), non-volatile RAM IP of its kind, utilizing the 'hot carrier effect' to...

111 12.0

MTP Non Volatile Memory for TSMC 180nm BCD Process NSCore's TwinBit(TM) is the only embedded CMOS, multi-time programmable (MTP), non-volatile RAM IP of its kind, utilizing the 'hot carrier effect' to ...

112 12.0

55nmHV MTP Non Volatile Memory for Standard CMOS Logic Process NSCore's TwinBit(TM) is the only embedded CMOS, multi-time programmable (MTP), non-volatile RAM IP of its kind, utilizing the 'hot carrier effect' to ...

113 0.0

9 track Near Threshold Voltage standard cell library at TSMC 55 nm TSMC 55 uLPeF, SESAME NTV, an extreme low voltage library designed to operate down to the minimum data retention voltage allowing users to share the s...

114 10.0

ONFI 3.0 Compatible I/O Buffer - TSMC 28 CLN28HPM Analog Bits ONFI 3.0 compatible I/O buffer provides a high-speed physical interface solution to support the increasing bandwidths demanded by today’s ...

115 10.0

Differential Receiver - TSMC 7FF Analog Bits Differential Signal Receiver macro is a receiver including on-chip termination, and addresses a large portfolio of applications. The Recei...

116 10.0

Differential Output Buffer - TSMC 6FF Analog Bits’ Differential Output Driver macros provide a low noise, high performance differential output clock. The output driver design implements a ...

117 10.0

Differential Output Buffer - TSMC N5 Analog Bits’ Differential Output Driver macros provide a low noise, high performance differential output clock. The output driver design implements a ...

118 10.0

Differential Signal Receiver - TSMC 6FF Analog Bits Differential Signal Receiver macro is a receiver including on-chip termination, and addresses a large portfolio of applications. The Recei...

119 10.0

Differential Signal Receiver - TSMC N5 Analog Bits Differential Signal Receiver macro is a receiver including on-chip termination, and addresses a large portfolio of applications. The Recei...

120 10.0

Glitch Detector - TSMC N5 Analog Bits’ Glitch Detector macro comprehensively addresses typical SOC power supply and other voltage glitch monitoring needs in a fully integrated ...

121 5.0556

A TSMC 65nm Wirebond IO library with 1-3.3V GPIO, 3.3V pulse-width modulation cell, I2C & SVID open-drain, 3.3V & 5V analog and OTP program cell Key attributes of our TSMC 65nm IO library include dual independent IO supply rails (1.0V-3.3V & 3.3V) and power-on-control (POC) to place IOs in a lo...

122 5.0556

A TSMC 180nm Flip-Chip IO library with 1.2-1.8V GPIO, 1.8V & 5V analog/RF, 20-36V ultra-low leakage low-cap HV analog and OTP program cell This silicon proven Certus 180 IO library is specifically tailored to address gaps in the native foundry IO offerings for this node. It features a 1....

123 4.0556

A GlobalFoundries 65nm Wirebond IO library with 2.5V GPIO, LVDS TX & RX and 2.5V analog / RF Key attributes of the GlobalFoundries 65nm IO library are dual selectable drive strengths and independent input & output enable / disable. The GPIO ce...

124 4.0556

LVDS RX & TX IOs in multiple foundry technology Certus provides full LVDS RX & TX IOs in GlobalFoundries and other foundry technologies. The Certus LVDS solutions are ANSI/TIA/EIA-644-A compliant a...

125 4.0556

High-voltage solutions in baseline TSMC and GlobalFoundries technology Certus is pleased to offer High-voltage ESD solutions across multiple baseline technologies. Distinguishing Certus is our ability to provide high-vol...

126 11.0

NVM OTP NeoBit in SHARP (180nm) eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...

127 11.0

NVM OTP NeoBit in Samsung (130nm) eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...

128 11.0

NVM OTP NeoBit in NEXCHIP (150nm, 110nm) eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...

129 11.0

NVM OTP NeoBit in Maxchip (180nm, 160nm, 150nm, 110nm, 90nm, 80nm) eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...

130 11.0

NVM OTP NeoBit in MagnaChip (350nm, 180nm, 150nm, 130nm, 110nm) eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...

131 11.0

NVM OTP NeoBit in JSC (130nm) eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...

132 11.0

NVM OTP NeoBit in Huali (55nm) eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...

133 11.0

NVM OTP NeoBit in HJTC (180nm, 160nm, 110nm) eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...

134 20.0

NVM OTP in Dongbu (180nm, 150nm, 110nm) Synopsys Non-Volatile Memory (NVM) IP provides reprogrammable NVM supporting up to 1 million bits (1Mbit) configurations in standard CMOS and BCD proc...

135 2.0

Single Port SRAM compiler - Memory optimized for ultra high density and high speed - compiler range up to 64 k Single Port SRAM compiler - TSMC 130 nm BCD Plus - Memory optimized for ultra high density and high speed - compiler range up to 64 k...

136 11.0

NVM OTP NeoBit in GTA (150nm) eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...

137 11.0

NVM OTP NeoBit in Grace (180nm, 160nm, 130nm, 110nm) eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...

138 11.0

NVM OTP NeoBit in GLOBALFOUNDRIES (350nm, 250nm, 180nm, 160nm, 150nm, 130nm, 110nm, 65nm, 55nm) eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...

139 11.0

NVM OTP NeoBit in Fujitsu (180nm) eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...

140 11.0

NVM OTP NeoBit in DongbuAnam (180nm, 160nm, 130nm, 110nm) eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...

141 11.0

NVM OTP NeoBit in CSMC (350nm, 250nm, 180nm, 160nm) eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...

142 11.0

NVM OTP NeoBit in CANSEMI (180nm, 110nm) eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...

143 11.0

NVM OTP NeoBit in ASMC (350nm) eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...

144 0.0

3DIO PHY IP for TSMC N5 Synopsys 3DIO is a specialized IO for multi-die integration. It includes multiple IP offerings for system-on-chip (SoC) designers to implement tunable...

145 0.0

Four Channel (4CH) LVDS Receiver in TSMC 40LP The MXL-LVDS-4CH-RX-T-40LP is a high-performance 4-channel LVDS Receiver implemented using digital CMOS technology. Both the serial and parallel data ...

146 0.0

TSMC embedded flash controller The eSi-TSMC-Flash IP core provides an AMBA 3 AHB-lite interface to TSMC's embedded flash macros....

147 10.0

LVDS IO handling data rate up to 50Mbps with maximum loading 60pF KA16UGLVDS01ST001 is a LVDS IO handling data rate up to 50Mbps with a maximum loading of 60pF. The differential voltage swing can be programmable from...

148 5.0

Inline CUP I/O The inline CUP I/O library provide 3.3V bi- directional I/O cells with pull -up, pull-down features, Schmitt trigger and a range of drive strengths....

149 0.0

3.125 Gbps DDR CML receiver 065TSMC_CML_01 core logic interface includes complementary output signal pins (OUTp, OUTn) for data transmission and enable pin EN_RX. PAD_INP and PAD...

150 0.0

3.125 Gbps DDR 1-channel CML transmitter 065TSMC_CML_02 core logic interface includes signal pins (INP1, INP2 and INN1, INN2) for data transmission, control pin EN_TX to configure transmitter...