1501 0.118

UMC 28nm HPC/RVT Logic and Mixed-Mode Process 12-track generic_core cell library (C40) UMC 28nm HPC/RVT Logic and Mixed-Mode Process 12-track generic_core cell library (C40)...

1502 0.118

UMC 28nm HPM/HVT Logic Process 12-track generic_core library with LMINUS (C30) UMC 28nm HPM/HVT Logic Process 12-track generic_core library with LMINUS (C30)...

1503 0.118

UMC 28nm HPM/HVT Logic Process 12-track generic_core library (C35) UMC 28nm HPM/HVT Logic Process 12-track generic_core library (C35)...

1504 0.118

UMC 28nm HPM/HVT Logic Process 12-track generic_core library with LPLUS (C38) UMC 28nm HPM/HVT Logic Process 12-track generic_core library with LPLUS (C38)...

1505 0.118

UMC 28nm HPM/LVT Logic Process 12-track generic cell library with LMINUS (C-31) UMC 28nm HPM/LVT Logic Process 12-track generic cell library with LMINUS (C-31)...

1506 2.0

SSTL_15 / SSTL_18 Combo I/O Pad Set The SSTL_15 / SSTL_18 library supports bidirectional single-ended and differential SSTL_15 and SSTL_18 signaling. The driver/receiver pairs, with emb...

1507 0.118

UMC 28nm HPM/LVT Logic Process 12-track generic cell library UMC 28nm HPM/LVT Logic Process 12-track generic cell library...

1508 0.118

UMC 28nm HPM/LVT Logic Process 12-track generic_core library with LPKUS (C38) UMC 28nm HPM/LVT Logic Process 12-track generic_core library with LPKUS (C38)...

1509 0.118

UMC 28nm HPM/RVT Logic Process 12-track generic_core library with LMINUS (C31) UMC 28nm HPM/RVT Logic Process 12-track generic_core library with LMINUS (C31)...

1510 0.118

UMC 28nm HPM/RVT Logic and Mixed-Mode Process 12-track generic cell library UMC 28nm HPM/RVT Logic and Mixed-Mode Process 12-track generic cell library...

1511 0.118

UMC 28nm HPM/RVT Logic Process 12-track generic cell library with LPLUS (C38) UMC 28nm HPM/RVT Logic Process 12-track generic cell library with LPLUS (C38)...

1512 0.118

UMC 28nm HPC/RVT Logic and Mixed-Mode Process 1.8V device RTC Core Library UMC 28nm HPC/RVT Logic and Mixed-Mode Process 1.8V device RTC Core Library...

1513 0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C90) UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C90)...

1514 0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60).W/O deep Nwell. UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60).W/O deep Nwell....

1515 0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60) w/ Forward Bias. W/ deep Nwell UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60) w/ Forward Bias. W/ deep Nwell...

1516 0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C90) w/ Forward Bias. W/ deep Nwell. UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C90) w/ Forward Bias. W/ deep Nwell....

1517 2.0

I2C IO Pad Set The I2C library provides the bidirectional I/O for two-line serial communication per Rev. 4 of the I2C-bus industry specification. The design is comp...

1518 0.118

UMC 55nm ULP/LVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60) UMC 55nm ULP/LVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60)...

1519 0.118

UMC 55nm ULP/RVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60). W/O deep Nwell UMC 55nm ULP/RVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60). W/O deep Nwell...

1520 0.118

UMC 55nm uLP/uHVT LowK Logic Process Ultra High Density (6T) Generic Core Cell Library UMC 55nm uLP/uHVT LowK Logic Process Ultra High Density (6T) Generic Core Cell Library...

1521 0.118

UMC 55nm ULP/uHVT Low-K Logic Process Process 6-track Generic Core Cell Library (C90) w/ Forward Bias. W/ deep Nwell. UMC 55nm ULP/uHVT Low-K Logic Process Process 6-track Generic Core Cell Library (C90) w/ Forward Bias. W/ deep Nwell....

1522 0.118

UMC 55nm eFlash/HVT Logic Process 7-track Genernic Core cell library UMC 55nm eFlash/HVT Logic Process 7-track Genernic Core cell library...

1523 0.118

UMC 55nm eFlash/LVT Logic Process 7-track Genernic Core cell library UMC 55nm eFlash/LVT Logic Process 7-track Genernic Core cell library...

1524 0.118

UMC 55nm eFlash/RVT Logic Process 7-track Genernic Core cell library UMC 55nm eFlash/RVT Logic Process 7-track Genernic Core cell library...

1525 0.118

UMC 40nm uLP/HVT Logic Process SYNS-like 7T GENERIC CORE Cell Library UMC 40nm uLP/HVT Logic Process SYNS-like 7T GENERIC CORE Cell Library...

1526 0.118

UMC 40nm uLP/LVT Logic Process SYNS-like 7T GENERIC CORE Cell Library UMC 40nm uLP/LVT Logic Process SYNS-like 7T GENERIC CORE Cell Library...

1527 0.118

UMC 40nm uLP/RVT Logic Process SYNS-like 7T GENERIC CORE Cell Library UMC 40nm uLP/RVT Logic Process SYNS-like 7T GENERIC CORE Cell Library...

1528 2.0

LPDDR2 / LPDDR3 / DDR3 / DDR3L / DDR3U / DDR4 Combo I/O Pad Set The LPDDR2/3_DDR3/4 library includes the combo driver/receiver cells with embedded power cells, the driver impedance calibration cell, and a full comp...

1529 0.118

UMC 28nm HPC/HVT Logic and Mixed-Mode Process 7-track Generic Core cell library enhanced for routing (C30) UMC 28nm HPC/HVT Logic and Mixed-Mode Process 7-track Generic Core cell library enhanced for routing (C30)...

1530 0.118

UMC 28nm HPC/HVT Logic and Mixed-Mode Process 7-track Generic Core cell library enhanced for routing (C35) UMC 28nm HPC/HVT Logic and Mixed-Mode Process 7-track Generic Core cell library enhanced for routing (C35)...

1531 0.118

UMC 28nm HPC/HVT Logic and Mixed-Mode Process 7-track Generic Core cell library enhanced for routing (C40) UMC 28nm HPC/HVT Logic and Mixed-Mode Process 7-track Generic Core cell library enhanced for routing (C40)...

1532 0.118

UMC 28nm HPC/LVT Logic and Mixed-Mode Process 7-track Generic Core cell library enhanced for routing (C30) UMC 28nm HPC/LVT Logic and Mixed-Mode Process 7-track Generic Core cell library enhanced for routing (C30)...

1533 0.118

UMC 28nm HPC/LVT Logic and Mixed-Mode Process 7-track Generic Core cell library enhanced for routing (C35) UMC 28nm HPC/LVT Logic and Mixed-Mode Process 7-track Generic Core cell library enhanced for routing (C35)...

1534 0.118

UMC 28nm HPC/LVT Logic and Mixed-Mode Process 7-track Generic Core cell library enhanced for routing (C40) UMC 28nm HPC/LVT Logic and Mixed-Mode Process 7-track Generic Core cell library enhanced for routing (C40)...

1535 0.118

UMC 28nm HPC/RVT Logic and Mixed-Mode Process 7-track Generic Core cell library enhanced for routing (C30) UMC 28nm HPC/RVT Logic and Mixed-Mode Process 7-track Generic Core cell library enhanced for routing (C30)...

1536 0.118

UMC 28nm HPC/RVT Logic and Mixed-Mode Process 7-track Generic Core cell library enhanced for routing (C35) UMC 28nm HPC/RVT Logic and Mixed-Mode Process 7-track Generic Core cell library enhanced for routing (C35)...

1537 0.118

UMC 28nm HPC/RVT Logic and Mixed-Mode Process 7-track Generic Core cell library enhanced for routing (C40) UMC 28nm HPC/RVT Logic and Mixed-Mode Process 7-track Generic Core cell library enhanced for routing (C40)...

1538 0.118

UMC 28nm HPM/HVT Logic and Mixed-Mode Process 7-track Genernic Core cell library with LMINUS (C31 HVT) UMC 28nm HPM/HVT Logic and Mixed-Mode Process 7-track Genernic Core cell library with LMINUS (C31 HVT)...

1539 2.0

SSTL with bi-directional I/O’s, Vref, and ODT for DDR2 memory (1.8 V) The DDR2 / DDR3 library includes the combo driver / receiver cells and a full complement of power and support cells for both single-ended and differen...

1540 0.118

UMC 28nm HPM/HVT Logic and Mixed-Mode Process 7-track generic core cell library UMC 28nm HPM/HVT Logic and Mixed-Mode Process 7-track generic core cell library...

1541 0.118

UMC 28nm HPM/HVT Logic and Mixed-Mode Process 7-track Genernic Core cell library with with LPLUS (C38 HVT) UMC 28nm HPM/HVT Logic and Mixed-Mode Process 7-track Genernic Core cell library with with LPLUS (C38 HVT)...

1542 0.118

UMC 28nm HPM/LVT Logic and Mixed-Mode Process 7-track Genernic Core cell library with LMINUS (C31 LVT) UMC 28nm HPM/LVT Logic and Mixed-Mode Process 7-track Genernic Core cell library with LMINUS (C31 LVT)...

1543 0.118

UMC 28nm HPM/LVT Logic and Mixed-Mode Process 7-track Generic Core cell library UMC 28nm HPM/LVT Logic and Mixed-Mode Process 7-track Generic Core cell library...

1544 0.118

UMC 28nm HPM/LVT Logic and Mixed-Mode Process 7-track Genernic Core cell library with with LPLUS (C38 LVT) UMC 28nm HPM/LVT Logic and Mixed-Mode Process 7-track Genernic Core cell library with with LPLUS (C38 LVT)...

1545 0.118

UMC 28nm HPM/RVT Logic and Mixed-Mode Process 7-track Genernic Core cell library with LMINUS (C31 RVT) UMC 28nm HPM/RVT Logic and Mixed-Mode Process 7-track Genernic Core cell library with LMINUS (C31 RVT)...

1546 0.118

UMC 28nm HPM/RVT Logic and Mixed-Mode Process 7-track generic core cell library UMC 28nm HPM/RVT Logic and Mixed-Mode Process 7-track generic core cell library...

1547 0.118

UMC 28nm HPM/RVT Logic and Mixed-Mode Process 7-track Genernic Core cell library with with LPLUS (C38 RVT) UMC 28nm HPM/RVT Logic and Mixed-Mode Process 7-track Genernic Core cell library with with LPLUS (C38 RVT)...

1548 0.118

UMC 80nm HV Process High Density Standard Cell Library UMC 80nm HV Process High Density Standard Cell Library...

1549 0.118

UMC 55nm eFlash/HVT LowK Logic Process 8-track Standard Core Library UMC 55nm eFlash/HVT LowK Logic Process 8-track Standard Core Library...

1550 2.0

7 way DDR combo The LPDDR2/3_DDR3/4 libraries contain the 7-way combo driver/receiver cells with embedded power cells, the driver impedance calibration cell, and the ...