2051 0.0

OTP One Time Programmable IP Nexchip 55HV_6V Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...

2052 0.0

OTP One Time Programmable IP Nexchip 110HV Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...

2053 0.0

OTP One Time Programmable IP Nexchip 110LP2 Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...

2054 0.0

OTP One Time Programmable IP SMIC 28HV Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...

2055 0.0

OTP One Time Programmable IP Samsung 90CIS Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...

2056 0.0

OTP One Time Programmable IP HLMC 55CIS Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...

2057 0.0

OTP One Time Programmable IP SMIC 153nm Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...

2058 0.0

OTP One Time Programmable IP XMC 55LL Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...

2059 0.3729

Dual Port SRAM Compiler with Row/Column Redundancy Option, with Low Leak support, short and long channel, inputs isolation, dual-rails, register scan, supports process FF/P Memory Compilers...

2060 0.3729

Dual Port SRAM Compiler with Row/Column Redundancy Option, with Low Leak support, short and long channel, inputs isolation, dual-rails, register scan, supports process FF/P Memory Compilers...

2061 0.118

Dual Port SRAM Compiler IP, UMC 0.13um SP/FSG process UMC 0.13um SP/FSG Logic process high density synchronous high density Dual Port (2RW) SRAM memory compiler....

2062 0.118

Dual Port SRAM Compiler IP, UMC 0.13um HS/FSG process UMC 0.13um HS/LL fusion (FSG) process high density synchronous high density Dual Port (2RW) SRAM memory compiler....

2063 0.118

Dual Port SRAM Compiler IP, Support Repair Features, UMC 65nm SP process UMC 65nm SP/RVT Logic and HVT Low-K process synchronous, high density, Dual Port SRAM compiler with the row redundancy option....

2064 0.118

Dual Port SRAM Compiler IP, UMC 0.11um HS/AE process UMC 0.11um HS/AE Logic process synchronous High-density Dual Port SRAM memory compiler....

2065 0.118

Dual Port SRAM Compiler IP, UMC 0.11um LL/AE process UMC 0.11um LL/AE (AL Advanced Enhancement) Logic process synchronous high density Dual Port SRAM memory compiler....

2066 0.118

Dual Port SRAM Compiler IP, UMC 0.11um HS/FSG process UMC 0.11um HS/RVT Logic process synchronous high density Dual Port SRAM memory compiler....

2067 0.118

Dual Port SRAM Compiler IP, UMC 0.153um MS process UMC 153nm Mixed-Mode/Logic process synchronous high density Dual Port SRAM memory compiler....

2068 0.118

Dual Port SRAM Compiler IP, UMC 0.18um MS process UMC 0.18um MM/RF process synchronous high density Dual Port SRAM memory compiler....

2069 0.118

Dual Port SRAM Compiler IP, UMC 55nm SP process UMC 55nm SP Low-K Logic process Low Power synchronous high density Dual Port SRAM memory compiler....

2070 0.118

Dual Port SRAM Compiler IP, Support Repair Features, UMC 55nm SP process UMC 55nm SP Low-K Logic process Low Power synchronous high density Dual Port SRAM memory compiler with redundancy....

2071 0.118

Dual Port SRAM Compiler IP, Support Repair Features, UMC 55nm SP process UMC 55nm 1.0V Standard Performance (SP) Low-K Logic process synchronous, high density, Dual Port SRAM with row redundancy option....

2072 0.118

Dual Port SRAM Compiler IP, UMC 55nm SP process UMC 55nm SP Low-K Logic process synchronous Dual Port RAM memory compiler....

2073 0.118

Dual Port SRAM Compiler IP, UMC 65nm SP process UMC 65nm 1.0V SP Low-K Logic process synchronous high density Dual Port SRAM compiler (with row redundancy option)....

2074 0.118

Dual Port SRAM Compiler IP, UMC 65nm LL process UMC 65nm low leakage RVT Logic Low_K process synchronous high density Dual Port SRAM memory compiler with bist testing interface....

2075 0.118

Dual Port SRAM Compiler IP, Support Repair Features, UMC 65nm LL process UMC 65nm low leakage RVT Logic Low_K process synchronous high density Dual Port SRAM memory compiler with redundancy elements and bist testing interfa...

2076 0.118

Dual Port SRAM Compiler IP, UMC 65nm LL process UMC 65nm low leakage RVT Logic Low_K process synchronous high density Dual Port SRAM memory compiler....

2077 0.118

Dual Port SRAM Compiler IP, Support Repair Features, UMC 65nm LL process UMC 65nm low leakage RVT Logic Low_K process synchronous high density Dual Port SRAM memory compiler wiht redundancy elements....

2078 0.118

Dual Port SRAM Compiler IP, UMC 90nm LL process UMC 90nm LL/RVT Low-K Logic process Synchronouslow AC power Dual Port SRAM....

2079 0.118

Dual Port SRAM Compiler IP, UMC 90nm LL process UMC 90nm LL/RVT Synchronous high density Dual Port SRAM memory compiler....

2080 0.3729

1.8V Secondary Oxide LVDS combo pad - TSMC 4nm 4FF/4P Dolphin's interface IP for standard I/O and specialty I/O delivers ultra high performance for DDR1/2/3/4, LPDDR2/3, DDR PHY, LVDS, LVPECL, I2C, PCI, S...

2081 0.3729

2.5V Secondary Oxide LVDS pad - TSMC 40nm 40G,LP,LP_eF,ULP,ULP_eF Dolphin's hardened DDR2/3/4 SDRAM PHY and LPDDR2/3 SDRAM PHY IP is a silicon-proven, Combo PHY supporting speeds up to 2133 Mbps. It is fully complian...

2082 0.3729

1.8V Secondary Oxide LVDS combo pad - TSMC 3nm Dolphin's interface IP for standard I/O and specialty I/O delivers ultra high performance for DDR1/2/3/4, LPDDR2/3, DDR PHY, LVDS, LVPECL, I2C, PCI, S...

2083 0.118

LVDS Rx IO IP, UMC 0.18um G2 process 0.13um LVDS RX IO PAD, UMC 0.13um HS/HVT-FSG process....

2084 0.118

LVDS Rx IO IP, UMC 90nm SP process 0.18UM RX (PAD), UMC 0.18um GII Logic process....

2085 0.118

LVDS Transmitter IP, Tx IO, UMC 55nm SP process 0.18um TX PAD, UMC 0.18um Logic RVT-FSG process....

2086 0.118

LVDS Receiver IP, 20MHz - 135MHz , UMC 0.18um G2 process DLL-based LVDS RX, VCC=3.3 for 20M~135MHz and VCC=2.5 for 20M~100MHz operation frequency, UMC 0.13um HS FSG Logic process....

2087 0.118

LVDS Transmitter IP, 8MHz - 135MHz , UMC 0.13um HS/FSG process 8M~135MHz DLL-based LVDS TX, UMC 0.13um HS/FSG process....

2088 0.118

LVDS Tx IO IP, UMC 90nm SP process LVDS TX Pad, UMC 0.35um Logic process....

2089 0.118

LVDS Transmitter IP, 700Mbps, UMC 90nm SP process 2.5V LVDS Transmitter 700Mbps, UMC 55nm SP Low-K Logic process....

2090 0.118

LVDS Receiver IP, UMC 90nm SP process DLL-based LVDS RX, UMC 55nm SP/RVT Low-K Logic process....

2091 0.118

LVDS Transmitter IP, 16MHz - 178MHz, UMC 55nm SP process 2.5V LVDS Transmitter 16~178MHz, UMC 55nm SP/RVT Low-K Logic process....

2092 0.118

LVDS Rx IO IP, 500Mbps, UMC 90nm LL process Low Power LVDS Receiver IO 500Mbps, UMC 55nm SP/RVT Low-K Logic process....

2093 0.118

LVDS Rx IO IP, UMC 0.18um Logic process LVDS RX IO, UMC 90nm SP/RVT Low-K Logic process....

2094 0.118

LVDS Transmitter IP, 8MHz - 135MHz, 4 channels, UMC 0.13um SP/FSG process 2.5V 4 channel LVDS Transmitter 8~135MHz, UMC 90nm SP/RVT Low-K process....

2095 0.118

LVDS Receiver IP, 8MHz - 135MHz, UMC 0.13um SP/FSG process 2.5V LVDS Receiver 8~135MHz, UMC 90nm SP process....

2096 0.118

LVDS Receiver IP, 700Mbps, UMC 0.13um SP/FSG process Low Power LVDS Receiver 700Mbps, UMC 90nm SP/RVT Low-K Logic process....

2097 0.118

LVDS Transmitter IP, 8MHz - 135MHz, UMC 90nm SP process 2.5V LVDS Transmitter 8~135MHz, UMC 90nm SP process....

2098 0.3729

A memory BIST solution which has been optimized for Dolphin memories Dolphin Technology now provides a memory BIST solution which has been optimized for Dolphin memories. It supports all Dolphin memory compilers, includ...

2099 0.3729

Pseudo 2 Ports SRAM Compiler with Row/Column Redundancy Option, with Low Leak support, short and long channel, inputs isolation, dual-rails, register scan, write assist, supports process FF/P Memory Compilers...

2100 0.3729

MultiBank Single Port SRAM Compiler with Row/Column Redundancy Option, with Low Leak support, short and long channel, inputs isolation, dual-rails, register scan, write assist, supports process FF/P Memory Compilers...