401 0.0

LogicFlash® Embedded MTP in Nexchip 150nm~55nm LogicFlash® MTP是一种基于CMOS工艺的嵌入式非挥发性存储器技术，基于逻辑工艺实现，无需增加额外光罩层次，或通过增加1层额外光罩，缩减IP面积，适合于1KB~64KB的中等容量应用，同时提供高达2万次的擦写次数。 LogicFlash®技术可以在0.18um到55nm的Logic/BC...

402 0.0

LogicFlash Pro® Embedded Flash memory IP LogicFlash Pro® eFlash是拥有自主知识产权的嵌入式闪存技术，可实现高性能、高可靠性的大容量存储。 产品开发验证中。...

403 0.0

Low Power MCU I/O This I/O library can easily support digital core voltage power off, and voltage transformation between different voltage domains. The common GPIOs con...

404 100.0

The SST SuperFlash® IP is an embedded CMOS Flash memory IP with sector/chip Erase and byte Program capability. SuperFlash® is SST’s patented and proprietary NOR flash technology. With 80B+ devices shipped, SuperFlash is the non-volatile memory of choice for emb...

405 0.0

Library of LVDS IOs cells for TSMC 40G The nSIO2000_TS40G_2V5_0V9 library is an IO cells library combining various LVDS and general purpose I/O powered at 2.5V/0.9V or 1.8V/0.9V, designed o...

406 0.0

TSMC 40G 2Gb/s RX LVDS IO cell The LSR25R/Z cell is a high-speed and low-power LVDS receiver IO cell powered at 2.5V/0.9V or 1.8V/0.9V, designed on the TSMC 40 G technology....

407 0.0

TSMC 40G 2Gb/s TX LVDS IO cell The LST25R/Z cell is a high-speed and low-power LVDS transmitter IO cell powered at 2.5V/0.9V or 1.8V/0.9V, designed on the TSMC 40 G technology....

408 0.0

TSMC 40G 2Gb/s bidirectional LVDS IO cell The LSB25R/Z cell is a high-speed and low-power LVDS bidirectional transceiver IO cell powered at 2.5V/0.9V or 1.8V/0.9V, designed on the TSMC 40 G te...

409 0.0

TSMC 40G Combo IO with 2Gb/s LVDS and CMOS GPIO A Combo cell is an IO cell combining an LVDS receiver, driver or transceiver with a double CMOS GPIO (in, out or bidirectional) powered at 2.5V/0.9V o...

410 0.3729

Ultra High Density and Ultra Low Power 7-track Standard cell library - TSMC 80nm GC/LP_eF Dolphin offers an extensive array of Standard Cell libraries that have been methodically tested and verified in silicon for each process technology su...

411 15.0

Library of LVDS IOs cells for TSMC 40LP The nSIO2000_TS40LP_2V5_1V1 library is an IO cells library combining various LVDS and general purpose I/O powered at 2.5V/1.1V or 1.8V/1.1V, designed ...

412 0.0

TSMC 40LP 2Gb/s RX LVDS IO cell The LSR25R/Z cell is a high-speed and low-power LVDS receiver IO cell powered at 2.5V/1.1V or 1.8V/1.1V, designed on the TSMC 40 LP technology....

413 0.0

TSMC 40LP 2Gb/s TX LVDS IO cell The LST25R/Z cell is a high-speed and low-power LVDS transmitter IO cell powered at 2.5V/1.1V or 1.8V/1.1V, designed on the TSMC 40 LP technology....

414 0.0

TSMC 40LP 2Gb/s bidirectional LVDS IO cell The LSB25R/Z cell is a high-speed and low-power LVDS bidirectional transceiver IO cell powered at 2.5V/1.1V or 1.8V/1.1V, designed on the TSMC 40 LP t...

415 0.0

TSMC 40LP Combo IO with 2Gb/s LVDS and CMOS GPIO A Combo cell is an IO cell combining an LVDS receiver, driver or transceiver with a double CMOS GPIO (in, out or bidirectional) powered at 2.5V/1.1V o...

416 0.0

Library of LVDS IOs cells for TSMC 65GP The nSIO2000_TS65GP_2V5_1V0 library is an IO cells library combining various LVDS and general purpose I/O powered at 2.5V/1.0V or 1.8V/1.0V, designed ...

417 0.0

TSMC 65GP 2Gb/s RX LVDS IO cell ...

418 0.0

TSMC 65GP 2Gb/s TX LVDS IO cell The LST25R/Z cell is a high-speed and low-power LVDS transmitter IO cell powered at 2.5V/1.0V or 1.8V/1.0V, designed on the TSMC 65 GP technology....

419 0.0

TSMC 65GP 2Gb/s bidirectional LVDS IO cell The LSB25R/Z cell is a high-speed and low-power LVDS bidirectional transceiver IO cell powered at 2.5V/1.0V or 1.8V/1.0V, designed on the TSMC 65 GP t...

420 0.0

TSMC 65GP Combo IO with 2Gb/s LVDS and CMOS GPIO A Combo cell is an IO cell combining an LVDS receiver, driver or transceiver with a double CMOS GPIO (in, out or bidirectional) powered at 2.5V/1.0V o...

421 0.3729

High Performance and High Density 10-track Standard cell library - TSMC 80nm GC/LP_eF Dolphin offers an extensive array of Standard Cell libraries that have been methodically tested and verified in silicon for each process technology su...

422 15.0

Library of LVDS IOs cells for TSMC 65LP The nSIO2000_TS65LP_2V5_1V2 library is an IO cells library combining various LVDS and general purpose I/O powered at 2.5V/1.2V or 1.8V/1.2V, designed ...

423 0.0

TSMC 65LP 2Gb/s RX LVDS IO cell The LSR25R/Z cell is a high-speed and low-power LVDS receiver IO cell powered at 2.5V/1.2V or 1.8V/1.2V, designed on the TSMC 65 LP technology....

424 0.0

TSMC 65LP 2Gb/s TX LVDS IO cell The LST25R/Z cell is a high-speed and low-power LVDS transmitter IO cell powered at 2.5V/1.2V or 1.8V/1.2V, designed on the TSMC 65 LP technology....

425 0.0

TSMC 65LP 2Gb/s bidirectional LVDS IO cell The LSB25R/Z cell is a high-speed and low-power LVDS bidirectional transceiver IO cell powered at 2.5V/1.2V or 1.8V/1.2V, designed on the TSMC 65 LP t...

426 0.0

TSMC 65LP Combo IO with 2Gb/s LVDS and CMOS GPIO A Combo cell is an IO cell combining an LVDS receiver, driver or transceiver with a double CMOS GPIO (in, out or bidirectional) powered at 2.5V/1.2V o...

427 11.0

NVM EEPROM NeoEE in SKHYNIX (180nm) eMemory's NeoEE IP is a cost-effective embedded EEPROM solution for both foundries & customers. No additional masks are required, and NeoEE gives foun...

428 11.0

NVM EEPROM NeoEE in Samsung (180nm, 130nm) eMemory's NeoEE IP is a cost-effective embedded EEPROM solution for both foundries & customers. No additional masks are required, and NeoEE gives foun...

429 11.0

NVM EEPROM NeoEE in NEXCHIP (150nm) eMemory's NeoEE IP is a cost-effective embedded EEPROM solution for both foundries & customers. No additional masks are required, and NeoEE gives foun...

430 11.0

NVM EEPROM NeoEE in Maxchip (180nm, 150nm, 90nm) eMemory's NeoEE IP is a cost-effective embedded EEPROM solution for both foundries & customers. No additional masks are required, and NeoEE gives foun...

431 11.0

NVM EEPROM NeoEE in MagnaChip (180nm, 130nm) eMemory's NeoEE IP is a cost-effective embedded EEPROM solution for both foundries & customers. No additional masks are required, and NeoEE gives foun...

432 0.3729

Thick oxide library - TSMC 80nm GC/LP_eF Dolphin offers an extensive array of Standard Cell libraries that have been methodically tested and verified in silicon for each process technology su...

433 11.0

NVM EEPROM NeoEE in HJTC (180nm) eMemory's NeoEE IP is a cost-effective embedded EEPROM solution for both foundries & customers. No additional masks are required, and NeoEE gives foun...

434 11.0

NVM EEPROM NeoEE in Grace (180nm, 160nm, 130nm, 110nm) eMemory's NeoEE IP is a cost-effective embedded EEPROM solution for both foundries & customers. No additional masks are required, and NeoEE gives foun...

435 11.0

NVM EEPROM NeoEE in GLOBALFOUNDRIES (180nm) eMemory's NeoEE IP is a cost-effective embedded EEPROM solution for both foundries & customers. No additional masks are required, and NeoEE gives foun...

436 11.0

NVM EEPROM NeoEE in CSMC (180nm, 160nm) eMemory's NeoEE IP is a cost-effective embedded EEPROM solution for both foundries & customers. No additional masks are required, and NeoEE gives foun...

437 11.0

NVM EEPROM NeoEE in TSMC (180nm, 160nm, 130nm) eMemory's NeoEE IP is a cost-effective embedded EEPROM solution for both foundries & customers. No additional masks are required, and NeoEE gives foun...

438 11.0

NVM MTP NeoMTP in UMC (180nm, 160nm, 110nm, 80nm, 55nm) NeoMTP is a single-poly embedded memory technology offering high NVM memory density with 1K endurance at the lowest implementation cost to be found in...

439 11.0

NVM MTP NeoMTP in Tower (180nm, 65nm) NeoMTP is a single-poly embedded memory technology offering high NVM memory density with 1K endurance at the lowest implementation cost to be found in...

440 11.0

NVM MTP NeoMTP in SMIC (180nm, 110nm) NeoMTP is a single-poly embedded memory technology offering high NVM memory density with 1K endurance at the lowest implementation cost to be found in...

441 11.0

NVM MTP NeoMTP in SKHYNIX (180nm, 130nm) NeoMTP is a single-poly embedded memory technology offering high NVM memory density with 1K endurance at the lowest implementation cost to be found in...

442 11.0

NVM MTP NeoMTP in JSC (130nm) NeoMTP is a single-poly embedded memory technology offering high NVM memory density with 1K endurance at the lowest implementation cost to be found in...

443 0.3729

Ultra High Density and Ultra Low Power 7-track Standard cell library - TSMC 90nm GT/G/LP_eF/LP Dolphin offers an extensive array of Standard Cell libraries that have been methodically tested and verified in silicon for each process technology su...

444 11.0

NVM MTP NeoMTP in HJTC (180nm) NeoMTP is a single-poly embedded memory technology offering high NVM memory density with 1K endurance at the lowest implementation cost to be found in...

445 11.0

NVM MTP NeoMTP in Grace (180nm) NeoMTP is a single-poly embedded memory technology offering high NVM memory density with 1K endurance at the lowest implementation cost to be found in...

446 11.0

NVM MTP NeoMTP in GLOBALFOUNDRIES (130nm) NeoMTP is a single-poly embedded memory technology offering high NVM memory density with 1K endurance at the lowest implementation cost to be found in...

447 11.0

NVM MTP NeoMTP in DongbuAnam (180nm) NeoMTP is a single-poly embedded memory technology offering high NVM memory density with 1K endurance at the lowest implementation cost to be found in...

448 11.0

NVM MTP NeoMTP in TSMC (180nm, 90nm) NeoMTP is a single-poly embedded memory technology offering high NVM memory density with 1K endurance at the lowest implementation cost to be found in...

449 11.0

NVM Anti-Fuse OTP NeoFuse in XMC (55nm) NeoFuse is a small-form factor logic NVM technology with the advantages of working on low power and being highly reliable and secure. It provides non-...

450 11.0

NVM Anti-Fuse OTP NeoFuse in Vanguard (150nm, 110nm) NeoFuse is a small-form factor logic NVM technology with the advantages of working on low power and being highly reliable and secure. It provides non-...