801 0.0

APC - Advanced Power Controller on GF 22FDSOI SGC21412_01_GF_22FDSOI is an Advanced Power Controller (APC) for integration in SoC. Including all the necessary auxiliary supply, monitoring, protect...

802 0.0

RTC and PMU Controller on GF 22FDSOI SGC22300_01_GF_22FDSOI is a Real Time Clock (RTC) based on the leading SGC21510 solution. Using advanced analog design techniques, to guarantee ultra-...

803 0.0

10-bit 1-channel 10 to 150 MSPS SAR ADC 055TSMC_ADC_13 is a 10-bit 1-channel SAR ADC with sample rate from 10 to 150 MSPS that operates with 1V peak-to-peak input signal. The block consists ...

804 0.0

Low-Dropout Linear Regulator (LDO) qLR-Aubrey-OV-ref-1.62-3.63-0.6-1.8.04_GF_22_FDX is a Linear regulator in GF 22FDX with ultra low quiescent current for retention applications....

805 99.0

TSMC CLN20SOC 20nm Clock Generator PLL - 700MHz-3500MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

806 0.0

TSMC CLN20SOC 20nm Clock Generator PLL - 350MHz-1750MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

807 0.0

TSMC CLN20SOC 20nm Clock Generator PLL - 175MHz-875MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

808 1.0

TSMC CLN28HPM 28nm Clock Generator PLL - 700MHz-3500MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

809 1.0

TSMC CLN28HPM 28nm Clock Generator PLL - 350MHz-1750MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

810 1.0

TSMC CLN28HPM 28nm Clock Generator PLL - 175MHz-875MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

811 1.0

TSMC CLN28HPL 28nm Clock Generator PLL - 440MHz-2200MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

812 1.0

TSMC CLN28HPL 28nm Clock Generator PLL - 220MHz-1100MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

813 1.0

TSMC CLN28HPL 28nm Clock Generator PLL - 110MHz-550MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

814 3.0

Low-Dropout Linear Regulator (LDO) qLR-Aubrey-ref-1.62-3.63-0.55-2.5.03_TSMC_40_uLPeF ultra-low quiescent LDO (Linear regulator) in TSMC 40uLPeF....

815 0.0

UMC L40G 40nm Clock Generator PLL - 680MHz-3400MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

816 0.0

UMC L40G 40nm Clock Generator PLL - 340MHz-1700MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

817 0.0

UMC L40G 40nm Clock Generator PLL - 170MHz-850MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

818 0.0

UMC L40LP 40nm Clock Generator PLL - 300MHz-1500MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

819 0.0

UMC L40LP 40nm Clock Generator PLL - 150MHz-750MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

820 0.0

UMC L40LP 40nm Clock Generator PLL - 75MHz-375MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

821 0.0

UMC L55LP 55nm Clock Generator PLL - 240MHz-1200MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

822 0.0

UMC L55LP 55nm Clock Generator PLL - 120MHz-600MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

823 0.0

UMC L55LP 55nm Clock Generator PLL - 60MHz-300MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

824 0.0

UMC L65LP 65nm Clock Generator PLL - 240MHz-1200MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

825 0.0

Low-Dropout Linear Regulator (LDO) The qLR-Aubrey-ref-1.62-3.63-1.2-3.3.01_TSMC_180_eLL is an ultra-low-quiescent-current regulator in TSMC 180eLL used to generate SoC internal supply f...

826 0.0

UMC L65LP 65nm Clock Generator PLL - 120MHz-600MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

827 0.0

UMC L65LP 65nm Clock Generator PLL - 60MHz-300MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

828 0.0

GF L28HPP 28nm Clock Generator PLL - 700MHz-3500MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

829 0.0

GF L28HPP 28nm Clock Generator PLL - 350MHz-1750MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

830 0.0

GF L28HPP 28nm Clock Generator PLL - 175MHz-875MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

831 0.0

GF L28SLP 28nm Clock Generator PLL - 440MHz-2200MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

832 0.0

GF L28SLP 28nm Clock Generator PLL - 220MHz-1100MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

833 0.0

GF L28SLP 28nm Clock Generator PLL - 110MHz-550MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

834 0.0

GF L55G 55nm Clock Generator PLL - 360MHz-1800MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

835 0.0

GF L55G 55nm Clock Generator PLL - 180MHz-900MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

836 3.0

Retention Alternative Regulator, combines high efficiency in normal mode and ultra-low quiescent current for sleep mode in GF 22FDX RAR-eSR-qLR-OV-ref-1.62-3.63-0.6-1.8.06_GF_22_FDX is a Retention Alternating Regulator in GF 22FDX combining two regulation sub-components: a high-eff...

837 0.0

GF L55G 55nm Clock Generator PLL - 90MHz-450MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

838 0.0

12bit 200Msps High Speed Pipeline ADC IP Core High performance, 12-bit resolution, 200Msps sample rate Mixed-signal IP, nodes up to 28nm. Leading edge systems on chip (SoCs) for wireline networkin...

839 0.0

12bit 320Msps High Speed Pipeline ADC IP Core 12-bit resolution, 320Msps sample rate Mixed-signal IP, nodes up to 28nm Silicon proven. Leading edge systems on chip (SoCs) for wireline networking, ...

840 0.0

12bit 2Gsps High Speed Pipeline ADC IP Core High performance, 12-bit resolution, 2 Gsps sample rate Pipeline ADC IP, nodes up to 28nm. Leading edge systems on chip (SoCs) for wireline networking...

841 0.0

14bit 1.3Gsps High Speed Sigma Delta ADC IP Core High performance, 14-bit resolution, 1.3Gsps sample rate Sigma Delta IP core, nodes up to 28nm Silicon proven. Leading edge systems on chip (SoCs) for...

842 0.0

14bit 3.2Gsps High Speed Sigma Delta ADC IP Core High performance, 14-bit resolution, 3.2Gsps sample rate Mixed-signal Sigma Delta IP, nodes up to 28nm Silicon proven. Leading edge systems on chip (S...

843 0.0

12bit 160Msps Ultra low power SAR ADC IP Core 12-bit resolution, 160Gsps sample rate Mixed-signal Ultra low power SAR ADC IP, nodes up to 28nm. Leading edge systems on chip (SoCs) for wireline net...

844 0.0

16bit 5Msps SAR General Purpose ADC IP Core The ADC IP offers a resolution of 16 bits and a sample rate of 5Msps at nodes of 40nm Silicon Proven. These components enable cutting-edge systems on ...

845 0.0

12bit 4Gsps SAR General Purpose ADC IP Core High performance, 12-bit resolution, 4 Gsps sample rate Mixed-signal General Purpose ADC IP, nodes up to 8nm. Leading edge systems on chip (SoCs) for ...

846 0.0

12bit 500Msps High Speed General Purpose SAR ADC IP Core High performance, 12-bit resolution, 500 Gsps sample rate Mixed-signal General Purpose SAR ADC IP Core, nodes up to 8nm. Leading edge systems on chip ...

847 0.0

9bit upto 3Msps Ultra low power SAR ADC IP core High performance, 9-bit resolution, upto 3 Msps sample rate Ultra Low Power Mixed-signal SAR ADC IP Core. Leading edge systems on chip (SoCs) for micr...

848 0.0

GF L55LP 55nm Clock Generator PLL - 320MHz-1600MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

849 0.0

10 bit 3Msps Ultra low power SAR ADC IP core High performance, 10-bit resolution, 3-Msps sample rate Ultra Low Power Mixed-signal SAR ADC IP Core. Leading edge systems on chip (SoCs) for microcon...

850 0.0

10bit 1Msps low power SAR ADC IP core High performance, 8-bit resolution, 1-Msps sample rate Ultra Low Power Mixed-signal SAR ADC IP Core Node available in 95nm. Leading edge systems on ch...