2001 1.0

UMC L180G 180nm Clock Generator PLL - 100MHz-500MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2002 1.0

UMC L150HS 150nm Clock Generator PLL - 70MHz-350MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2003 1.0

UMC L150HS 150nm Clock Generator PLL - 140MHz-700MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2004 1.0

UMC L180G 180nm Clock Generator PLL - 50MHz-250MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2005 0.0

GF L28SLP 28nm DDR DLL - 246MHz-1230MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

2006 1.0

UMC L130SP 130nm Clock Generator PLL - 118MHz-590MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2007 1.0

UMC L180G 180nm Spread Spectrum PLL - 200MHz-1000MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2008 1.0

UMC L180G 180nm Spread Spectrum PLL - 100MHz-500MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2009 1.0

UMC L180G 180nm Spread Spectrum PLL - 50MHz-250MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2010 1.0

UMC L150HS 150nm Spread Spectrum PLL - 280MHz-1400MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2011 1.0

UMC L150HS 150nm Spread Spectrum PLL - 140MHz-700MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2012 1.0

UMC L150HS 150nm Spread Spectrum PLL - 70MHz-350MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2013 1.0

UMC L130HS 130nm Spread Spectrum PLL - 320MHz-1600MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2014 1.0

UMC L130HS 130nm Spread Spectrum PLL - 160MHz-800MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2015 1.0

UMC L130HS 130nm Spread Spectrum PLL - 80MHz-400MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2016 0.0

GF L28SLP 28nm DDR DLL - 156MHz-780MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

2017 1.0

TSMC CL018G 180nm Spread Spectrum PLL - 220MHz-1100MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2018 1.0

TSMC CL018G 180nm Spread Spectrum PLL - 110MHz-550MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2019 1.0

TSMC CL018G 180nm Spread Spectrum PLL - 55MHz-275MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2020 1.0

TSMC CL018E 180nm Spread Spectrum PLL - 260MHz-1300MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2021 1.0

TSMC CL018E 180nm Spread Spectrum PLL - 130MHz-650MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2022 1.0

TSMC CL018E 180nm Spread Spectrum PLL - 65MHz-325MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2023 1.0

TSMC CL015G 150nm Spread Spectrum PLL - 260MHz-1300MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2024 1.0

TSMC CL015G 150nm Spread Spectrum PLL - 130MHz-650MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2025 1.0

TSMC CL015G 150nm Spread Spectrum PLL - 65MHz-325MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2026 1.0

TSMC CL015LV 150nm Spread Spectrum PLL - 280MHz-1400MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2027 5.0

Power On Reset / Brown Out Reset POR-BOR-1.62-3.63-0.55-3.3.02_TSMC_22_ULL is a combined Power-On-Reset and Brown-Out-Reset in TSMC 22ULL....

2028 0.0

GF L28SLP 28nm DDR DLL - 117MHz-585MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

2029 1.0

TSMC CL015LV 150nm Spread Spectrum PLL - 140MHz-700MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2030 1.0

TSMC CL015LV 150nm Spread Spectrum PLL - 70MHz-350MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2031 1.0

TSMC CL013G 130nm Spread Spectrum PLL - 272MHz-1360MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2032 1.0

TSMC CL013G 130nm Spread Spectrum PLL - 136MHz-680MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2033 1.0

TSMC CL013G 130nm Spread Spectrum PLL - 68MHz-340MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2034 1.0

TSMC CL013LV 130nm Spread Spectrum PLL - 320MHz-1600MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2035 1.0

TSMC CL013LV 130nm Spread Spectrum PLL - 160MHz-800MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2036 1.0

TSMC CL013LV 130nm Spread Spectrum PLL - 80MHz-400MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2037 1.0

TSMC CL013G 130nm Clock Generator PLL - 272MHz-1360MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2038 1.0

TSMC CL015LV 150nm Clock Generator PLL - 280MHz-1400MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2039 0.0

GF L55G 55nm DDR DLL - 196MHz-980MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

2040 1.0

TSMC CL015G 150nm Clock Generator PLL - 260MHz-1300MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2041 1.0

TSMC CL018E 180nm Clock Generator PLL - 260MHz-1300MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2042 1.0

TSMC CL018G 180nm Clock Generator PLL - 220MHz-1100MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2043 1.0

UMC L130HS 130nm Clock Generator PLL - 320MHz-1600MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2044 1.0

UMC L150HS 150nm Clock Generator PLL - 280MHz-1400MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2045 1.0

UMC L180G 180nm Clock Generator PLL - 200MHz-1000MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2046 1.0

TSMC CL013LV 130nm Deskew PLL - 320MHz-1600MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2047 1.0

TSMC CL013G 130nm Deskew PLL - 272MHz-1360MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2048 1.0

TSMC CL015LV 150nm Deskew PLL - 280MHz-1400MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2049 1.0

TSMC CL015G 150nm Deskew PLL - 260MHz-1300MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2050 0.0

GF L55G 55nm DDR DLL - 124MHz-620MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...