2051 1.0

TSMC CL015LV 150nm Spread Spectrum PLL - 140MHz-700MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2052 1.0

TSMC CL015LV 150nm Spread Spectrum PLL - 70MHz-350MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2053 1.0

TSMC CL013G 130nm Spread Spectrum PLL - 272MHz-1360MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2054 1.0

TSMC CL013G 130nm Spread Spectrum PLL - 136MHz-680MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2055 1.0

TSMC CL013G 130nm Spread Spectrum PLL - 68MHz-340MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2056 1.0

TSMC CL013LV 130nm Spread Spectrum PLL - 320MHz-1600MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2057 1.0

TSMC CL013LV 130nm Spread Spectrum PLL - 160MHz-800MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2058 1.0

TSMC CL013LV 130nm Spread Spectrum PLL - 80MHz-400MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2059 1.0

TSMC CL013G 130nm Clock Generator PLL - 272MHz-1360MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2060 1.0

TSMC CL015LV 150nm Clock Generator PLL - 280MHz-1400MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2061 0.0

GF L55G 55nm DDR DLL - 196MHz-980MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

2062 1.0

TSMC CL015G 150nm Clock Generator PLL - 260MHz-1300MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2063 1.0

TSMC CL018E 180nm Clock Generator PLL - 260MHz-1300MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2064 1.0

TSMC CL018G 180nm Clock Generator PLL - 220MHz-1100MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2065 1.0

UMC L130HS 130nm Clock Generator PLL - 320MHz-1600MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2066 1.0

UMC L150HS 150nm Clock Generator PLL - 280MHz-1400MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2067 1.0

UMC L180G 180nm Clock Generator PLL - 200MHz-1000MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2068 1.0

TSMC CL013LV 130nm Deskew PLL - 320MHz-1600MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2069 1.0

TSMC CL013G 130nm Deskew PLL - 272MHz-1360MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2070 1.0

TSMC CL015LV 150nm Deskew PLL - 280MHz-1400MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2071 1.0

TSMC CL015G 150nm Deskew PLL - 260MHz-1300MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2072 0.0

GF L55G 55nm DDR DLL - 124MHz-620MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

2073 1.0

TSMC CL018E 180nm Deskew PLL - 260MHz-1300MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2074 1.0

TSMC CL018G 180nm Deskew PLL - 220MHz-1100MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2075 1.0

UMC L130HS 130nm Deskew PLL - 320MHz-1600MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2076 1.0

UMC L130SP 130nm Deskew PLL - 236MHz-1180MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2077 1.0

UMC L150HS 150nm Deskew PLL - 280MHz-1400MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2078 1.0

UMC L180G 180nm Deskew PLL - 200MHz-1000MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2079 1.0

UMC L150HS 150nm Deskew PLL - 140MHz-700MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2080 1.0

UMC L130SP 130nm Deskew PLL - 118MHz-590MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2081 1.0

UMC L130HS 130nm Clock Generator PLL - 80MHz-400MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2082 1.0

UMC L130HS 130nm Clock Generator PLL - 160MHz-800MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2083 0.0

GF L55G 55nm DDR DLL - 93MHz-465MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

2084 1.0

UMC L130SP 130nm Clock Generator PLL - 236MHz-1180MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2085 1.0

UMC L130SP 130nm Spread Spectrum PLL - 59MHz-295MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2086 1.0

UMC L130SP 130nm Spread Spectrum PLL - 118MHz-590MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2087 1.0

UMC L130SP 130nm Spread Spectrum PLL - 236MHz-1180MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2088 1.0

TSMC CL013LVOD 130nm Clock Generator PLL - 440MHz-2200MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2089 1.0

TSMC CLN90G 90nm Clock Generator PLL - 320MHz-1600MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2090 1.0

TSMC CL013LVOD 130nm Clock Generator PLL - 110MHz-550MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2091 1.0

TSMC CL013LVOD 130nm Clock Generator PLL - 220MHz-1100MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2092 1.0

TSMC CLN90G 90nm Clock Generator PLL - 80MHz-400MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2093 1.0

TSMC CLN90G 90nm Clock Generator PLL - 160MHz-800MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2094 0.0

GF L55LP 55nm DDR DLL - 164MHz-820MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

2095 1.0

TSMC CLN90G 90nm Deskew PLL - 80MHz-400MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2096 1.0

TSMC CLN90G 90nm Deskew PLL - 160MHz-800MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2097 1.0

TSMC CLN90G 90nm Deskew PLL - 320MHz-1600MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2098 1.0

TSMC CL013LVOD 130nm Deskew PLL - 110MHz-550MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2099 1.0

TSMC CL013LVOD 130nm Deskew PLL - 220MHz-1100MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2100 1.0

TSMC CL013LVOD 130nm Deskew PLL - 440MHz-2200MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...