4051 0.0

TSMC CLN40LP+ 40nm DDR DLL - 177MHz-885MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

4052 0.0

TSMC CLN40LP+ 40nm DDR DLL - 112MHz-560MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

4053 0.0

TSMC CLN40LP+ 40nm DDR DLL - 84MHz-420MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

4054 0.0

TSMC CLN28HPC+ 28nm DDR DLL - 347MHz-1735MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

4055 0.0

TSMC CLN28HPC+ 28nm DDR DLL - 220MHz-1100MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

4056 8.0

Ultra-low jitter, low-power ring-oscillator-based PLL - 4.5GHz-9.5GHz InCirT’s APLL9GGF22 is the ring-oscillator based analogue-PLL which provides ultra-low jitter (690fs rms jitter at 9.5GHz) and low-power consumption (...

4057 0.0

TSMC CLN28HPC+ 28nm DDR DLL - 165MHz-825MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

4058 0.0

TSMC CLN16FFCLL 16nm DDR DLL - 395MHz-1975MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

4059 0.0

TSMC CLN16FFCLL 16nm DDR DLL - 250MHz-1250MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

4060 7.0

Ultra-Low Power 6 - 13 Bit 0.5 -10 kS/s 10μW Analog Front End The Analog-Frontend (AFE) IP consists of programmable current and voltage preamplifier followed by a Successive Approximation Register (SAR) architect...

4061 0.0

TSMC CLN16FFCLL 16nm DDR DLL - 188MHz-940MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

4062 0.0

TSMC CLN16FF+LL 16nm DDR DLL - 395MHz-1975MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

4063 0.0

TSMC CLN16FF+LL 16nm DDR DLL - 250MHz-1250MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

4064 0.0

TSMC CLN16FF+LL 16nm DDR DLL - 188MHz-940MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

4065 0.0

TSMC CLN16FF+GL 16nm DDR DLL - 395MHz-1975MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

4066 0.0

TSMC CLN16FF+GL 16nm DDR DLL - 250MHz-1250MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

4067 0.0

TSMC CLN16FF+GL 16nm DDR DLL - 188MHz-940MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

4068 0.0

TSMC CL016G 160nm DDR DLL - 120MHz-600MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

4069 0.0

TSMC CL016G 160nm DDR DLL - 76MHz-380MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

4070 0.0

TSMC CL016G 160nm DDR DLL - 57MHz-285MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

4071 8.0

IGAPLLV01A, TSMC CLN16FF+LL Spread Spectrum Clock Generator PLL IGAPLLV01A is a Spread Spectrum Phase Lock Loop (SSPLL), without external components and is designed to provide stable and accurate clock. The IGAPL...

4072 0.0

GF L40LP 40nm DDR DLL - 177MHz-885MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

4073 0.0

GF L40LP 40nm DDR DLL - 112MHz-560MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

4074 0.0

GF L40LP 40nm DDR DLL - 84MHz-420MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

4075 0.0

UMC L28HPC 28nm General Purpose PLL - 350MHz-1750MHz The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...

4076 0.0

TSMC CLN85LP 90nm General Purpose PLL - 120MHz-600MHz The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...

4077 0.0

TSMC CLN65ULP 65nm General Purpose PLL - 100MHz-500MHz The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...

4078 0.0

TSMC CLN40ULP 40nm General Purpose PLL - 75MHz-375MHz The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...

4079 0.0

TSMC CLN40LP+ 40nm General Purpose PLL - 150MHz-750MHz The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...

4080 0.0

TSMC CLN28HPC+ 28nm General Purpose PLL - 360MHz-1800MHz The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...

4081 0.0

TSMC CLN16FFCLL 16nm General Purpose PLL - 400MHz-2000MHz The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...

4082 8.0

IGAPLLV03A, TSMC CLN16FF+ General Purpose PLL The IGAPLLV03A is a General purpose Phase Lock Loop (PLL), without external components and is designed to provide stable and accurate clock. The IGAPL...

4083 0.0

TSMC CLN16FF+LL 16nm General Purpose PLL - 400MHz-2000MHz The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...

4084 0.0

TSMC CLN16FF+GL 16nm General Purpose PLL - 400MHz-2000MHz The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...

4085 0.0

GF L40LP 40nm General Purpose PLL - 150MHz-750MHz The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...

4086 0.0

UMC L28HPC 28nm Clock Generator PLL - 700MHz-3500MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

4087 0.0

UMC L28HPC 28nm Clock Generator PLL - 350MHz-1750MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

4088 0.0

UMC L28HPC 28nm Clock Generator PLL - 175MHz-875MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

4089 0.0

TSMC CLN85LP 90nm Clock Generator PLL - 240MHz-1200MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

4090 0.0

TSMC CLN85LP 90nm Clock Generator PLL - 120MHz-600MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

4091 0.0

TSMC CLN85LP 90nm Clock Generator PLL - 60MHz-300MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

4092 0.0

TSMC CLN65ULP 65nm Clock Generator PLL - 200MHz-1000MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

4093 10.0

Temperature Sensor with Digital Output High accuracy thermal sensing for reliability and optimisation), TSMC 16FFC A high precision low power junction temperature sensor that has been developed to be easily embedded into digital ASIC designs. The block features an ...

4094 8.0

IGATHMS04A, TSMC CLN40LP Thermal Sensor ADC The IGATHMS04A is a temperature sensor building in internal analog-to-digital converter with 10bit resolution which can be applied for temperature and...

4095 0.0

TSMC CLN65ULP 65nm Clock Generator PLL - 100MHz-500MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

4096 0.0

TSMC CLN65ULP 65nm Clock Generator PLL - 50MHz-250MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

4097 0.0

TSMC CLN40ULP 40nm Clock Generator PLL - 150MHz-750MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

4098 0.0

TSMC CLN40ULP 40nm Clock Generator PLL - 75MHz-375MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

4099 0.0

TSMC CLN40ULP 40nm Clock Generator PLL - 37MHz-187MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

4100 0.0

TSMC CLN40LP+ 40nm Clock Generator PLL - 300MHz-1500MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...