51 100.0

UCIe-S PHY for Standard Package (x16) in TSMC (N7, N6, N4P, N5, N3) Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...

52 100.0

UCIe-A PHY for Advanced Package (x64) in TSMC (N7, N6, N5, N3) Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...

53 10.0

Die-to-Die, 112G Ultra-Extra Short Reach PHY in TSMC (12nm, N7, N6, N5) The Synopsys XSR PHY IP for 112Gbps per lane die-to-die connectivity enables high-bandwidth ultra and extra short reach interfaces in multi-chip modul...

54 10.0

Die-to-Die, 112G Ultra-Extra Short Reach PHY in GF (12nm) The Synopsys XSR PHY IP for 112Gbps per lane die-to-die connectivity enables high-bandwidth ultra and extra short reach interfaces in multi-chip modul...

55 10.0

Die-to-Die Controller IP The Synopsys Die-to-Die Controller IP, optimized for latency, bandwidth, power and area, enables efficient inter-die connectivity in server, AI accele...

56 100.0

Universal Chiplet Interconnect Express (UCIe) Controller Synopsys UCIe Controller IP is comprised of the Die-to-Die Adapter layer and Protocol layer for widely used protocols such as PCI Express and CXL. The...

57 0.0

UCIe Controller for Streaming Protocols Synopsys UCIe Controller IP is comprised of the Die-to-Die Adapter layer and Protocol layer for widely used protocols such as PCI Express and CXL. The...

58 0.0

UCIe-A PHY for Advanced Package (x64) in Samsung (SF4X) Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...

59 0.0

UCIe-A PHY for Advanced Package (x64) in TSMC (N5) Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...

60 0.0

UCIe-A PHY for Advanced Package (x64) in Samsung (SF2) Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...

61 0.0

UCIe-S PHY for Standard Package (x32) in TSMC (N3P) Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...

62 0.0

UCIe PHY IP on TSMC N3P Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...

63 70.0

40G UCIe PHY IP on Samsung SF4X Synopsys UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale data center, AI,...

64 9.0308

UCIe 2.0 PHY for Standard Package (8nm) The UCI Express Specification Revision 2.0 supports high-speed serialization and deserialization at 4GT/s, 8GT/s, 12GT/s, 16GT/s, and 24GT/s with a 64...

65 8.5077

UCIe 2.0 PHY for Advanced Package (8nm) The UCI Express Specification Revision 2.0 supports high-speed serialization and deserialization at 4GT/s, 8GT/s, 12GT/s, 16GT/s, and 24GT/s with a 64...

66 0.0

Automotive-Compliant Synopsys UCIe Controller IP Synopsys UCIe Controller IP is comprised of the Die-to-Die Adapter layer and Protocol layer for widely used protocols such as PCI Express and CXL. The...

67 0.0

Interface Controller - PHY IP The UCIE PHY IP is a market leading, extremely low-power, low-latency interface IP for very high bandwidth connections between two dies that are on th...

68 0.0

UCIe Standard Package PHY on Samsung S8LPU The UCIE PHY IP is a market leading, extremely low-power, low-latency interface IP for very high bandwidth connections between two dies that are on th...

69 0.0

UCIe Standard Package PHY on Samsung S14LPP The UCIE PHY IP is a market leading, extremely low-power, low-latency interface IP for very high bandwidth connections between two dies that are on th...

70 8.5077

UCIe 2.0 PHY for Standard Package (4nm) The UCI Express Specification Revision 2.0 supports high-speed serialization and deserialization at 4GT/s, 8GT/s, 12GT/s, and 16GT/s with a 16-lane co...

71 0.0

UCIe-S (Gen2) Compatible PHY for Standard Package (x16) in TSMC (N3P) Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...

72 16.0

Die-2-die interfaces for chiplets - GPIOs for 2.5D and 3D integration Analog I/O and on-chip Electrostatic Discharge (ESD) protection. Proven on many foundries: TSMC, UMC, GF, TowerSemi, Samsung Foundry, ... Proven in ...

73 0.0

Innovative Ultra-High-Speed Chiplet Solution Innosilicon INNOLINK™ IP provides a leading-edge chiplet solution allowing massive amounts of low-latency data to pass seamlessly between smaller chip...

74 0.0

Nutcracker XSR Connectivity Chiplet Core and analog logic may not always deploy at the same time in the same process. Maturing high performance analog typically takes longer in moving to...

75 60.0

Multi-Die interLink (GLink 2.3) IP GUC multi-die interLink (GLink) IP provides world’s best class solution for high-bandwidth, low-power, low-latency multi-channel interconnection in a ...

76 0.0

Interconnect Technology EXTOLL introduces a new interconnection network architecture for High-Performance Computing, which brings a rich set of features to the HPC applicatio...

77 0.0

Chiplet Solution Based on the traditional advantages of SerDes and DDR IP, KNiulink Semiconductor has launched a solution that meets the UCIe standard based on local r...

78 0.0

UMI™ for Die-to-Memory (D2M) PHY IP Unlike fixed unidirectional die-to-die solutions, NuLink technology is able to deliver low-power and high-performance D2M solutions....

79 11.0

Die-to-Die (D2D) Interconnect Lightweight die-to-die interconnect solution optimized for highest performance with the lowest power and area overhead...

80 15.0

Coherent Network-on-Chip (NoC) SkyeChip's NoC is the first in the world that is able to reconfigure routing paths after tapeout. It is a scalable and area efficient interconnect sol...

81 10.0

Mobiveil RapidIO Controller (GRIO) Mobiveil Generic RapidIO (GRIO) controller is a highly flexible and configurable IP to provide RapidIO interface on one side and a generic interface o...

82 7.0

Non-Coherent Network-on-Chip (NoC) SkyeChip's NoC is the first in the world that is able to reconfigure routing paths after tapeout. Performance (throughput and latency) optimized no...

83 45.0

FlexNoC® 5 Interconnect IP FlexNoC® Interconnect IP by Arteris is used by the world’s top semiconductor design teams as the backbone for on-chip communications in chips that tar...

84 14.0

40G Ultralink D2D PHY for GF12LP+ Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...

85 14.0

40G Ultralink D2D PHY for Samsung 7LPP Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...

86 14.0

Universal Chiplet Interconnect Express (UCIe 1.0) Controller Ultra-low latency UCIe controller for standard industry chiplet interoperability on streaming, PCIe, and CXL protocols The Cadence UCIe™ Controller i...

87 30.0

Coherent Network-on-chip (NoC) IP C-NoC is a layered, scalable, configurable, and physically aware configurable NoC. It supports mesh, grid and torus topologies with simultaneous exist...

88 0.0

Die-to-Die PHY Eliyan uses its NuLink technology to develop die-to-die PHY IP products to support multiple standards (including UCIe and BoW) and multiple packaging ...

89 45.0

FlexWay® Interconnect IP Arteris FlexWay® 5 network-on-chip (NoC) IP is particularly well suited to cost-efficient, low-power IoT edge devices and microcontrollers (MCUs). ...

90 60.0

Ncore™ Coherent NoC IP Built on more than a decade of volume silicon, Ncore™ is silicon-proven coherent NoC IP that is highly configurable, power-efficient, and works with a...

91 45.0

CodaCache® Last Level Cache IP CodaCache® addresses modern design challenges through performance-optimized caching, efficient data access, and power optimization techniques. It also...

92 5.0556

VX16: 600Mbps low-power D2D interface, TSMC 16nm FFC/FFC+ A custom, low-power die-to-die interface in TSMC 16nm FFC/FFC+. The bidirectional I/O cell (VX_HSIO) runs in two modes: standard full rail-to-rail swi...

93 5.0556

UD28: <4gnps low-power die-to-die interface, TSMC 28nm A silicon-proven, low-power die-to-die interface in TSMC 28nm (HPM/HPC/HPC+) for flip-chip / multi-die assembly. Separate TX-only and RX-only cells ru...

94 45.0

XL and 2XL Options for FlexNoC® 5 and FlexGen® The XL and 2XL Options extend the capabilities of FlexNoC 5 and FlexGen, enabling designers to develop small to large-scale network-on-chip (NoC) topo...

95 0.0

NoC Generator A web-based NOC configuration tool for generating and simulating Coherent and Non-Coherent NoCs...

96 30.0

High speed NoC (Network On-Chip) Interconnect IP OPENEDGES is the only total memory system IP company providing both memory controller and on-chip interconnect. OIC is the ORBIT high-speed On-chip In...

97 0.0

Low Power Dual PHY for UCIe low cost robust Chiplets YorChip UniPHY™ Dual PHY is a flexible version of YorChip's multi-protocol PHY which supports UCIe and BOW standards. The Dual PHY's uni...

98 0.0

5/10/40G Ultra Low Latency MAC PCS with AXI-4 and UCIe support This IP is optimized for AI/ML workloads and lowest possible latency.It is not meant to be a generic 1G to 10G MAC – it only supports 5G and 10G...

99 0.0

Blumind Chiplet Contact us to learn more about Neural Signal Processor known-good-die for system in package integration....

100 0.0

Interconnect fabric IP with cache coherence support StarNoC-700 is StarFive's self-developed high-scalable, high-performance interconnect fabric IP supporting cache coherence, enabling the construction ...