1 5.0

DDR4IO for memory PHY, 3200Mbps The DDR4 IO is used to transfer the Command/Address/Clk and Data between the memory controller PHY and the DRAM device. The TX is designed to send inf...

2 0.0

GUC HBM2 Controller and PHY IP GUC HBM2 IP is a complete solution for SoC design targeting high bandwidth applications such as AI, HPC, data centers and networking. GUC HBM2 IP is f...

3 40.0

LPDDR5X/5/4X/4 combo PHY at 7nm OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...

4 50.0

ONFI 3.2 NV-DDR2 PHY in GDSII Compliant to ONFI 3.2 electrical interface, Arasan ONFI 3.2 PHY, delivered in hard macro, is process technology proven and easy to integrate. This ON...

5 100.0

ONFI 4.2 Controller Arasan Chip System’s (ACS) Open NAND Flash Interface (ONFI) Host Controller is designed to provide the next generation of high speed interaction with ...

6 70.0

LPDDR6/5X/5/4X/4 combo PHY at Samsung SF5A OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...

7 0.0

NVM Express (NVMe) Controller (compliant with NVMe 1.4 Base Specification) The NVM Express (NVMe) controller is compliant with NVMe 1.4 Base Specification. Most of NVMe feature supported to achieve well compatibility, SRIOV i...

8 10.0

SD 4.1 SDIO 4.1 Host Controller IP The SD 4.1/SDIO 4.1 IP from Arasan Chip Systems is a highly integrated host controller IP solution that supports two key memory card I/O technologies:...

9 20.0

SD 4.1 UHS-II PHY for TSMC 12nm FF The rapid proliferation of high-performance mobile and handheld devices has resulted in increasing requirements for non-volatile memory. Memory interf...

10 20.0

LPDDR4/3, DDR4/3 Memory Controller IP OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...

11 70.0

DDR4/3, LPDDR5x/5/4x/4 Memory Controller IP OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...

12 20.0

GDDR6 Memory Controller IP OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...

13 20.0

High Performance HBM, HBM3 Memory Controller OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...

14 20.0

SD 4.0 UHS-II PHY TSMC 28nm HPM North-South SD 4.0 (UHS-II) achieves a peak interface speed of 3.12 Gbps. Arasan’s UHS-II PHY is compliant with the specification of UHS-II and is an extremely ar...

15 0.0

DDR3 Controller IP The AXI DDR3 Controller provides access to DDR3 memory. It accepts the Read / Write commands from AXI and converts it into DDR3 access. While doing th...

16 70.0

LPDDR6/5X/5/4X/4 Memory Controller IP OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...

17 20.0

LPDDR4 multiPHY V2 in Samsung (14nm, 11nm, 10nm, 8nm) The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...

18 1.0

eMMC 5.1 HS400 PHY and I/O Pads in TSMC 28HPC PLUS Arasan provides a HS400 compatible PHY that customers can integrate with the HS400 I/O PADs. It is designed to optimize I/O performance with a core v...

19 0.0

Synopsys LPDDR Controller for LPDDR6, LPDDR5X and LPDDR5 Synopsys LPDDR6/5X/5 Controller IP is a next generation controller optimized for power, latency, bandwidth, and area, supporting JEDEC standard LPDDR6...

20 0.0

Synopsys HBM4 Controller IP Solution The Synopsys HBM4 Controller IP is optimized for power, latency, bandwidth, and area, supporting the JEDEC HBM4 standard. It interoperates with Synops...

21 0.0

DDR Controller supporting DDR5 RDIMM and MRDIMM Gen2 with Advanced Feature Package The Synopsys DDR5 MRDIMM2 Controller IP is a next-generation memory controller designed to deliver optimal latency, bandwidth, and area efficiency. It...

22 2.0

eMMC 5.1 HS400 PHY and I/O Pads in TSMC 16FF-NS Arasan provides a HS400 compatible PHY that customers can integrate with the HS400 I/O PADs. It is designed to optimize I/O performance with a core v...

23 0.0

eMMC 5.1 HS400 PHY and I/O Pads in TSMC 16FF PLUS Arasan provides a HS400 compatible PHY that customers can integrate with the HS400 I/O PADs. It is designed to optimize I/O performance with a core v...

24 5.0

eMMC 5.1 HS400 PHY and I/O Pads in TSMC 16FF PLUS LL Arasan provides a HS400 compatible PHY that customers can integrate with the HS400 I/O PADs. It is designed to optimize I/O performance with a core v...

25 5.0

eMMC 5.1 HS400 PHY and I/O Pads in TSMC 16FFC NS Arasan provides a HS400 compatible PHY that customers can integrate with the HS400 I/O PADs. It is designed to optimize I/O performance with a core v...

26 50.0

ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 12nm The NAND Flash landscape is changing and the Arasan NAND Flash Controller IP Core is changing in accordance with it. New applications are emerging and...

27 75.0

ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 16nm The NAND Flash landscape is changing and the Arasan NAND Flash Controller IP Core is changing in accordance with it. New applications are emerging and...

28 50.0

ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 28nm The NAND Flash landscape is changing and the Arasan NAND Flash Controller IP Core is changing in accordance with it. New applications are emerging and...

29 25.0

ONFI 5.0 Controller Arasan Chip System’s NAND flash controller IP provides easy, reliable access to an off-chip NAND flash. It supports all modes of the Open NAND Flash I...

30 5.0

ONFI 5.0 PHY Open NAND Flash Interface (ONFI) for NAND Flash Memory chips is an open standard. Arasan’s ONFI 5.0 PHY IP is designed to connect seamlessly with thei...

31 20.0

LPDDR4 multiPHY V2 in TSMC (28nm, 22nm, 16nm, 12nm) The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...

32 60.0

IGAHBMV03A, TSMC CLN16FFC HBM PHY with CoWoS technology IGAHBMV03A, TSMC CLN16FFC HBM PHY with CoWoS technology...

33 60.0

TSMC CLN16FFGL+ HBM PHY IP This datasheet describes GUC’s HBM (High Bandwidth Memory) PHY IP, which can be integrated with HBM memory controller to provide HBM functionality. Th...

34 60.0

TSMC CLN5FF HBM PHY IP This datasheet describes GUC HBM (High Bandwidth Memory) PHY IP, which could be integrated with HBM memory controller to provide HBM functionality. Th...

35 8.0

TSMC CLN7FF HBM2E PHY IP This datasheet describes GUC HBM (High Bandwidth Memory) PHY IP, which could be integrated with HBM memory controller to provide HBM functionality. Th...

36 0.0

HBM2 Memory Controller HBM2 Memory Controller...

37 0.0

HBM2E Memory Controller HBM2E Memory Controller...

38 0.0

HBM3 Memory Controller HBM3 Memory Controller...

39 10.0

GDDR6 PHY IP for 12nm OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...

40 50.0

LPDDR5/4x/4 combo PHY on 14nm, 12nm OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...

41 20.0

LPDDR4X multiPHY in TSMC (16nm, 12nm,N7, N6) The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...

42 0.0

DDR3 SDRAM Memory Controller The logiMEM DDR3 SDRAM Memory Controller is a size optimized, flexible, parametric and synthesizable Synchronous DRAM Controller that supports industr...

43 0.0

LPDDR5X/5/4X Controller with Inline Memory Encryption (IME) Security Module Synopsys LPDDR5X/5/4X Controller is a next generation controller optimized for power, latency, bandwidth, and area, supporting JEDEC standard LPDDR5X,...

44 0.0

AHB Parallel Flash Controller The AHB Parallel Flash Controller allows an AHB Master (usually a CPU) to read, program, or erase the connected arrangement of external parallel Super...

45 0.0

HBM3 PHY IP on TSMC N5 The Synopsys HBM3 PHY is a complete physical layer IP interface (PHY) solution for high-performance computing (HPC), AI, graphics, and networking ASIC...

46 6.0

ONFI : Open NAND Flash Interface Host Controller NAND Flash Interface controller that provides the means for a system to be designed that supports a range of NAND Flash devices without direct design ...

47 6.0

SD Memory Card Host Controller VinSDHC3_0 SD Host Controller Core controls data transfers between the SD Host System and the SD Memory Card sockets. It is compliant with the standar...

48 10.0

DDR2/DDR3/DDR3L/LPDDR2 I/O Buffer - TSMC 40 CLN40LP Analog Bits impedance programmable I/O buffer provides a high-speed physical interface solution to support the increasing bandwidths demanded by today...

49 0.0

SDIO Device IP SDIO DEVICE interface provides full support for the SDIO DEVICE synchronous serial interface, compatible with SD specification part E1 SDIO 4.10. Thro...

50 0.0

SDIO Host IP SDIO HOST interface provides full support for the SDIO HOST CONTROLLER synchronous serial interface, compatible with SDIO version 4.10 specification....