551 0.118

Single Port SRAM Compiler IP, UMC 55nm SP process UMC 55nm SP Low-K Logic process Low Power synchronous high density Single Port SRAM memory compiler....

552 0.118

Single Port SRAM Compiler IP, Support Repair Features, UMC 55nm SP process UMC 55nm SP Low-K Logic process Low Power synchronous high density Single Port SRAM memory compiler with redundancy....

553 0.118

Single Port SRAM Compiler IP, UMC 55nm SP process UMC 55nm SP/RVT Low-K Logic process synchronous Low Power (PG-DC) using 0.425-Bit cell Single Port SRAM memory compiler....

554 0.3729

DDRI/II/III SSTL/HSTL combo interface with RTT (rectangle) - TSMC 55nm 55GP,LP,LP_EMF,ULP,ULP_EMF Dolphin's hardened DDR2/3/4 SDRAM PHY and LPDDR2/3 SDRAM PHY IP is a silicon-proven, Combo PHY supporting speeds up to 2133 Mbps. It is fully complian...

555 0.118

Single Port SRAM Compiler IP, UMC 55nm SP process UMC 55nm SP/RVT+HVT Low-K Logic process synchronous high density Single Port SRAM memory compiler....

556 0.118

Single Port SRAM Compiler IP, UMC 55nm SP process UMC 55nm SP Low-K Logic process synchronous ultra high speed Single Port SRAM memory compiler....

557 0.118

Single Port SRAM Compiler IP, UMC 55nm SP process UMC 55nm SP Low_K Logic process synchronous high density Single Port SRAM memory compiler....

558 0.118

Single Port SRAM Compiler IP, Support Repair Features, UMC 55nm SP process UMC 55nm SP Low_K Logic process synchronous high density Single Port SRAM memory compiler with row-pair redundancy....

559 0.118

Single Port SRAM Compiler IP, UMC 65nm SP process UMC 65nm SP Low-K Logic process synchronous high density Single Port SRAM memory compiler....

560 0.118

Single Port SRAM Compiler IP, Support Repair Features, UMC 65nm SP process UMC 65nm SP Low-K Logic process synchronous high density Single Port SRAM with redundaycy memory compiler....

561 0.118

Single Port SRAM Compiler IP, Support Repair Features, UMC 65nm LL process UMC 65nm LL/RVT Low-K process synchronous high density, Single Port SRAM compiler with the row redundancy....

562 0.118

Single Port SRAM Compiler IP, UMC 65nm LL process UMC 65nm LL/RVT Low-K Logic process 1-port high density memory compiler....

563 0.118

Single Port SRAM Compiler IP, Support Repair Features, UMC 90nm SP process UMC 90nm SP/ Low-K Logic process Synchronous high density Single Port SRAM compiler With Redundancy....

564 0.118

Single Port SRAM Compiler IP, Support Repair Features, UMC 90nm SP process UMC 90nm SP/RVT Low-K Logic process Single Port SRAM (Introduce Redundancy feature to the existing FSD0A_B_SH)....

565 0.3729

DDRI/II/III SSTL/HSTL combo interface with RTT (square) - TSMC 55nm 55GP,LP,LP_EMF,ULP,ULP_EMF Dolphin's hardened DDR2/3/4 SDRAM PHY and LPDDR2/3 SDRAM PHY IP is a silicon-proven, Combo PHY supporting speeds up to 2133 Mbps. It is fully complian...

566 0.118

Single Port SRAM Compiler IP, Support Repair Features, UMC 90nm LL process UMC 90nm LL/RVT Low-K Logic process Synchronous high density Single Port SRAM compiler With Redundancy....

567 0.118

Single Port SRAM Compiler IP, UMC 90nm LL process UMC 90nm Logic process low leakage devices synchronous Low Power Single Port hihg density memory compiler....

568 0.0

32/64-bit PC133 SDRAM Controller The 32/64-bit PC133 SDRAM Controller” controller handles PC133 SDRAM compatible memory devices attached to a 32 or 64 bit wide data bus. The cont...

569 0.0

32-bit SSRAM/PROM Controller The 32-bit SSRAM/PROM Controller IP cores is an 32-bit SSRAM/PROM/IO controller that interfaces external Synchronous pipelined SRAM, PROM, and I/O to ...

570 0.0

Combined PROM/IO/SRAM/SDRAM Memory controller with EDAC The FTMCTRL can handle four types of devices: PROM, asynchronous static ram (SRAM), synchronous dynamic ram (SDRAM) and memory mapped I/O devices (I/O...

571 0.0

QUAD SPI Memory controller The core maps a memory device connected via the Serial Peripheral Interface (SPI) into AMBA AHB address space. Reading memory is performed by directly...

572 1.0

HBM3/2E Combo PHY&Controller The third-generation HBM (HBM3/2E) technology, outlined by the JESD235C standard, inherits physical 128-bit DDR interface with 2n/4n prefetch architec...

573 1.0

HBM2E PHY&Controller Innosilicon HBM2E PHY IP is a silicon proven product with max speed up to 3600Mbps per DQ data, HBM2E memory has 1024bit DQ, total bandwidth can be 3....

574 0.3729

SDRAM DDR3/2 & LPDDR3/2 Hardened PHY - TSMC 65nm 65GP,LP,LP_EMF Dolphin s hardened DDRx SDRAM PHY and LPDDRx SDRAM PHY IP is a silicon-proven, Combo PHY supporting speeds up to 2133 Mbps. It is fully compliant with...

575 1.0

HBM2E/2 Combo PHY&Controller Innosilicon HBM2E/2 Combo PHY provides turnkey physical interface solutions for ICs requiring access to JEDEC compatible HBM devices. It is optimized ...

576 2.0

HBM3, HBM3E PHY & Controller This document describes a general layout scheme and Innosilicon HBM3/3E PHY connecting to the controller using a DFI digital interface. All interface ...

577 0.0

ONFI INNOSILICON™ ONFI IP provides a connectivity solutions for ICs requiring access to ONFI-compatible NAND Flash devices. Optimized for low-power and hig...

578 30.0

NVM Express Host IP Core The IPM-NVMe_Host core is a verilog IP to be integrated in a FPGA or ASIC design. It fully manages the NVMe and PCIe protocol on the host side without...

579 30.0

create easily your own PCIe NVMe SSD This architecture proposal is based on NVMe and NAND Flash Controller offloaded IPs. It is integrated in a FPGA and could be also be integrated in ASI...

580 30.0

add encryption, compression ... in your datas This architecture proposal is based on NVMe offloaded IPs. It is integrated in a FPGA and could be also be integrated in ASIC, allowing to provide des...

581 5.0

NVME Host IP The new NVME-HOST-IP of Logic Design Solutions enables now random access in addition to the existing sequential access and multi-user access. FAT32 fi...

582 5.0

Artix Ultra Scale Plus NVMe Host IP Gen4 The LDS NVME HOST IP has been done for beginners and expert in NVMe to drive NVMe PCIe SSD. - The LDS NVME HOST IP provides two interfaces : o One C...

583 70.0

Universal NVM Express Controller (UNEX) Mobiveil's Universal NVM Express Controller (UNEX) is highly flexible and configurable design targeted for both Enterprise and client class solutions ...

584 50.0

PCIe Gen5 NVMe SSD RAMDISK Reference Platform Mobiveil’s RAMDISK-Gen5is a PCIe Gen5 and 1.4 NVMe compliant Ramdisk that emulates the next generation NVMe Gen5 SSDs with high performance. With hi...

585 0.3729

DDRI/II/III SSTL/HSTL combo interface without RTT (rectangle) - TSMC 65nm 65GP,LP,LP_EMF Dolphin's hardened DDR2/3/4 SDRAM PHY and LPDDR2/3 SDRAM PHY IP is a silicon-proven, Combo PHY supporting speeds up to 2133 Mbps. It is fully complian...

586 20.0

LPDDR4x/4 PHY IP for 22nm OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...

587 40.0

LPDDR5X/5/4X/4 PHY IP for 12nm The LPDDR5X/5/4X/4 combo PHY IP features a state-of-art mixed-signal architecture that addresses the challenges of DRAM integration in high-performan...

588 40.0

LPDDR5X/5/4X/4 PHY for 16nm The LPDDR5X/5/4X/4 combo PHY IP features a state-of-art mixed-signal architecture that addresses the challenges of DRAM integration in high-performan...

589 20.0

LPDDR5X/5/4X/4 combo PHY at 12nm The LPDDR5X/5/4X/4 combo PHY IP features a state-of-art mixed-signal architecture that addresses the challenges of DRAM integration in high-performan...

590 0.0

Read-Modify-Write Core The Read-Modify-Write (RMW) Core from Rambus handles misaligned bursts when an Error Correction Code (ECC) is being used. An ECC code word must be ca...

591 0.0

Multi-Port Front-End The Rambus Multi-Port Front-End Core from Rambus provides a multi-port interface to Rambus Memory Controller Cores. Each user request is provided wit...

592 0.0

Reorder Core The Reorder Core from Rambus reorders requests based on first on priority and second on throughput optimization. Throughput optimization includes m...

593 200.0

GDDR7 Memory Controller The Rambus GDDR7 controller core is designed for use in applications requiring high memory throughput including graphics, high performance computing (...

594 200.0

LPDDR5T / LPDDR5X / LPDDR5 Controller The Rambus LPDDR5 Controller supporting LPDDR5T, LPDDR5X, LPDDR5 controller core is designed for use in applications requiring high memory throughput ...

595 180.0

HBM4 Memory Controller The Rambus HBM4 Controller Core is designed for use in applications requiring high memory bandwidth and low latency including AI/ML, HPC, advanced dat...

596 0.3729

DDRI/II/III SSTL/HSTL combo interface with RTT (rectangle) - TSMC 65nm 65GP,LP,LP_EMF Dolphin's hardened DDR2/3/4 SDRAM PHY and LPDDR2/3 SDRAM PHY IP is a silicon-proven, Combo PHY supporting speeds up to 2133 Mbps. It is fully complian...

597 0.0

NVMe expansion The Flash MX IP Core implements a hardware accelerator for zstd compression and decompression. Compute-intensive software-based compression is offload...

598 0.0

TSMC CLN12FFCLL 12nm DDR3 PHY - 2133Mbps The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individ...

599 0.0

TSMC CLN12FFCLL 12nm DDR4 PHY - 4266Mbps The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individ...

600 0.0

TSMC CLN12FFCLL 12nm DDR5 PHY - 6400Mbps The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individ...