51 1.0

USB 2.0 OTG Controller - SMIC 55nm Eflash ...

52 1.0

USB1.1 PHY - SMIC 55nm Eflash ...

53 1.0

USB 2.0 PHY - SMIC 55nm Eflash ...

54 1.0

USB 2.0 PHY - SMIC 55nm Eflash ...

55 1.0

USB3.0 PHY - SMIC 55nm Eflash High speed analog circuits for USB3.0 PHY application 745um*620um...

56 20.0

PCIe 5.0 PHY IP for Storage and High-Bandwidth Connection M31 PCIe 5.0 PHY IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications. The PCIe 5.0 IP suppo...

57 1.0

USB2.0 PHY - SMIC130nm Eflash ...

58 1.0

USB1.1 PHY - SMIC130nm Eflash ...

59 1.0

USB2.0 PHY - SMIC 110nm generic ...

60 1.0

USB1.1 PHY - SMIC 180nm ...

61 1.0

USB1.1 PHY - HHGrace 110nm ULL ...

62 0.0

1.5G MIPI D-PHY in SMIC 130nm~28nm The ACTT family of interface IP for MIPI protocols is leading the way with mobile-optimized low power and high performance. Compliant with the specifi...

63 0.0

2.5G MIPI D-PHY in HLMC 28nm The ACTT family of interface IP for MIPI protocols is leading the way with mobile-optimized low power and high performance. Compliant with the specifi...

64 0.0

2.5G MIPI D-PHY in TSMC 22nm The ACTT family of interface IP for MIPI protocols is leading the way with mobile-optimized low power and high performance. Compliant with the specifi...

65 0.0

6.25G SerDes in 55nm The Actt's 6.25G SerDes IP is a 4-Channel Serdes configuration with 1 PLL, 4 TX channels and 4 RX channels. It’s based on SMIC 55nm embedded-flash tec...

66 0.0

16G SerDes in 28nm The Actt's 16G SerDes IP is a high performance Multi-lane SerDes PHY IP designed for chips that perform high bandwidth data communication while operat...

67 20.0

MIPI C-PHY v2.0 /D-PHY v2.5 Combo IP MIPI D-PHY is a serial interface technology which is widely adopted in smartphones and other multimedia enabled mobile devices. To further improve thr...

68 5.0

Single Wire Protocol (SWP) slave digital controller compliant with the ETSI 102.613 standard The Single Wire Protocol (SWP) Slave Digital Controller is a fully integrated protocol manager intended to interface the UICC (SWP slave) to the NFC c...

69 5.0

Single Wire Protocol (SWP) Master Analog Front End (AFE) compliant with the ETSI 102.613 standard The Single Wire Protocol (SWP) Master Analog Front End (AFE) is a fully integrated interface intended to connect the NFC chip (SWP master) to the UICC...

70 5.0

Single Wire Protocol (SWP) Slave Analog Front End (AFE) compliant with the ETSI 102.613 standard The Single Wire Protocol (SWP) Slave Analog Front End (AFE) is a fully integrated interface intended to connect the UICC (SWP slave) to the NFC chip (...

71 4.0

NVMe-to-SATA Bridge The IntelliProp IPP-NV186A-BR is an NVMe-to-SATA Bridge that utilizes the IntelliProp NVMe Target IP Core and the IntelliProp SATA AHCI Host Core to c...

72 4.0

Gen-Z Responder IP Core The IntelliProp IPC-GZ189A-DT Gen-Z Responder is an IP Core that allows the building of Gen-Z compliant media devices. The IPC-GZ189A-DT is compliant ...

73 4.0

Gen-Z Requester IP Core The IntelliProp IPC-GZ190A-HI Gen-Z Requester is an IP Core that allows companies to build Gen-Z compliant Requester devices. The IPC-GZ190A-HI is com...

74 4.0

Gen-Z Physical Layer for 802.3 IP Core The IntelliProp IPC-GZ196A-ZM Gen-Z Physical Layer for 802.3 is an IP Core that allows companies to attach a Gen-Z core to an 802.3 Phy. The IPC-GZ196...

75 4.0

Gen-Z Physical Layer for PCIe IP Core The IntelliProp IPC-GZ197A-ZM Gen-Z Physical Layer for PCIe is an IP Core that allows companies to attach a Gen-Z core to a PCIe Phy. The IPC-GZ197A-Z...

76 4.0

Gen-Z Link Layer IP Core The IntelliProp IPC-GZ198A-ZM Gen-Z Link Layer is an IP Core that allows companies to build Gen-Z compliant devices. The IPC-GZ198A-ZM is compliant wi...

77 4.0

SATA Host AHCI Core The IntelliProp SATA Host AHCI (IPC-SA156A-HI) is an industry standard Serial-ATA (SATA) host interface core that enables customers to use high throug...

78 100.0

Low-Latency SerDes PMA - 10GbE, 25GbE Best(lowest)-in-class latency 10GbE/25GbE SerDes PMA....

79 4.0

SATA Bridge Platform (Optional: AES, Hardware Datapath) The IntelliProp SATA Bridge Platform is an extensible IP Core which encompasses a SATA Device core, a SATA Host core, along with an embedded processor...

80 4.0

SAS 1-to-1 Speed Bridge with Sandbox The IntelliProp SAS Bridge with Sandbox (IPP-SS115A-BR) design provides SAS compliant connections to a SAS host and a SAS device. The host and device ...

81 4.0

Gen-Z Switch IP Core The IntelliProp IPC-GZ201A-ZM Gen-Z Switch is an IP Core that allows companies to build Gen-Z compliant components. The IPC-GZ201A-ZM is compliant wit...

82 0.0

SATA Port Multiplier with Sandbox The IntelliProp IPP-SA128A-PM (SATA Port Multiplier with Sandbox) device is an IP core that provides SATA Port Multiplier functionality with support f...

83 5.0

MIPI DSI-2 Transmitter Interface IP MIPI DSI-2 (Display Serial Interface) defines an interface between a peripheral device (camera) and host processor (application engine) for mobile dev...

84 15.0

Multi-Video-Source Multiplexing Serial Video Transmitter for MIPI CSI2 The SVT-CS4AP2 supports MIPI CSI2 over MIPI D-PHY. It allows mutilplexing of up to 10 video sources into a CSI2 output stream...

85 13.0

Multiplexing transceiver with 4 CSI2 inputs and a single CSI2 output This IP multiplexes inputs from up to 4 CSI2 cameras, each with up to 4 data lanes, to a single CSI2 output stream, with up to 4 lanes. It comprises o...

86 15.0

MIPI CSI2 rev 2.0 transmitter/controller for FPGA, with 8 lanes and 2.5Gbps per lane The SVTPlus-CSI2-F is a second generation MIPI CSI2-Tx transmitter IP core for FPGA implementations. It complies with MIPI® CSI2 V2.0 and DPHY1.2 spec...

87 15.0

2.5Gbps Per Lane MIPI-CSI2 Compliant Serial Video Transmitter The SVTPlus supports a clock lane and 4 data lanes, each lane featuring at up to 2.5Gbps, for a total of 10Gbps. The highly parallel architecture of t...

88 25.0

2.5Gbps Per Lane MIPI-CSI2 Compliant Serial Video Receiver The SVRPlus supports a clock lane and 4 data lanes, each lane featuring at up to 2.5Gbps, for a total of 10Gbps. The highly parallel architecture of...

89 100.0

Multi-protocol SerDes PMA - PCIe1 PCIe2 PCIe3 PCIe4 PCIe5 and more Multiprotocol SerDes PMA supporting variety of interfaces....

90 16.0

AHB-Lite APB4 Bridge The Roa Logic AHB-Lite APB4 Bridge is a fully parameterized soft IP interconnect bridge between the AMBA 3 AHB-Lite v1.0 and AMBA APB v2.0 bus protoco...

91 16.0

AHB-Lite Multilayer Switch The Roa Logic AHB-Lite Multi-layer Interconnect is a fully parameterized High Performance, Low Latency Interconnect Fabric soft IP for AHB-Lite. It al...

92 16.0

APB4 Multiplexer The AMBA APB v2.0 bus protocol – commonly referred to as APB4 – defines a low-cost interface that is optimized for minimal power consumption and redu...

93 16.0

AHB-Lite General Purpose Memory Module The Roa Logic AHB-Lite Memory IP is a fully parameterized soft IP implementing on-chip memory for access by an AHB-Lite based Master. All signals defi...

94 16.0

APB4 General Purpose Input/Output Module The APB4 GPIO Core is fully parameterised core designed to provide a user-defined number of general purpose, bidirectional IO to a design. The IO a...

95 16.0

AHB-Lite Timer The Roa Logic AHB-Lite Timer IP is a fully parameterized soft IP implementing a user-defined number of timers and functions as specified by the RISC-V...

96 16.0

RISC-V Compliant Platform Level Interrupt Controller Fully Parameterized & Programmable Platform Level Interrupt Controller (PLIC) for RISC-V based Processor Systems supporting a user-defined number of i...

97 23.0

Display Stream Compression (DSC 1.2) Decoder The Trilinear Technologies Display Stream Compression (DSC) Decoder core offers realtime decompression of high-definition streams with resolutions fro...

98 23.0

Display Stream Compression (DSC 1.2) Encoder The Trilinear Technologies Display Stream Compression (DSC) Encoder offers real-time compression of high-definition streams with resolutions up to 8K....

99 2.5

SATA Host 6G Controller on Kintex 7 The LDS SATA 3 HOST XK7 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Kintex 7 speed grade 2 FPGA. The LDS SATA 3 ...

100 23.0

MST Topology Management Stack The Trilinear Technologies DisplayPort Multi-stream Transport (MST) Topology Management Software enables developers to accelerate software development...