501 14.0

MIPI CSI-2 TX Controller for v2.1 CSI-2 transmitter controller for application processor The Cadence® Transmitter (TX) Controller IP for MIPI DSI is compliant with the MIPI® Alliance ...

502 14.0

I3C Controller Controller IP for the MIPI I3C interface The Cadence® IP Family for MIPI® Protocols delivers area-optimized interface IP with the low power and high ...

503 14.0

MIPI D-PHY for TSMC D-PHY physical layer Developed by experienced teams with industry-leading domain expertise and extensively validated by multiple hardware platforms, ...

504 14.0

PCI Express (PCIe) 5.0 Controller Application-optimized, high-performance controller IP for PCIe The Cadence® Controller IP for PCIe 5.0 provides the logic required to integrate a roo...

505 14.0

PCI Express (PCIe) 4.0 Controller Application-optimized, high-performance controller IP for PCIe The Cadence® Controller IP for PCIe 4.0 provides the logic required to integrate a roo...

506 2.0

MIPI D-PHY TSMC 40LP eDRAM Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...

507 14.0

PCI Express (PCIe) 3.1 Controller Application-optimized, high-performance controller IP for PCIe The Cadence® Controller IP for PCIe® 3.1 is a solution created for mobile applications...

508 14.0

USB 2.0 PHY for TSMC Proven PHY IP for USB Device, Host, and OTG with small footprint and low active power The ubiquity of USB 2.0 in devices makes it nearly mandatory fo...

509 101.0

MIPI C-PHY/D-PHY Combo CSI-2 RX+ IP (6.0Gsps/trio, 4.5Gbps/lane) in TSMC N6 The MXL-CDPHY-6p0G-CSI-2-RX+-T-N6 is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specificat...

510 23.0

MIPI C-PHY TRx(80-2500Msps) / MIPI D-PHY TRx(80-4500Mbps) Combo PHY 5nm The MIPI D-PHY/C-PHY Combo IP supports data rates of up to 4.5Gbps for D-PHY and 2.5Gsps for C-PHY. It operates in High-Speed (HS), Low-Power (LP), an...

511 14.0

40G Ultralink D2D PHY for Samsung 7LPP Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...

512 23.0

MIPI C-PHY TRx(80-8000Msps) / MIPI D-PHY TRx(80-9000Mbps) Combo PHY 4nm The MIPI D-PHY/C-PHY Combo IP supports data rates of up to 9Gbps for D-PHY and 8Gsps for C-PHY. It operates in High-Speed (HS), Low-Power (LP), and Es...

513 14.0

40G Ultralink D2D PHY for GF12LP+ Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...

514 2.0

MIPI D-PHY - UMC 55eHV Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...

515 14.0

UltraLink Controller Ultralink controller for high performance die-to-die interconnect on streaming, CXS, and AXI protocols The Cadence Ultralink Controller enables a pro...

516 14.0

Universal Chiplet Interconnect Express (UCIe 1.0) Controller Ultra-low latency UCIe controller for standard industry chiplet interoperability on streaming, PCIe, and CXL protocols The Cadence UCIe™ Controller i...

517 15.0

PCIe 5.0 PHY With sophisticated architecture and advanced technology, KNiulink SerDes PHY IP with PMA and PCS layer is designed for low power and high performance ...

518 10.0

PCIe 4.0 PHY With sophisticated architecture and advanced technology, KNiulink SerDes PHY IP with PMA and PCS layer is designed for low power and high performance ...

519 8.0

PCIe 3.0/2.0 PHY With sophisticated architecture and advanced technology, KNiulink PCIE GEN3/GEN2 PHY IP with PMA and PCS layer is designed for low power and high perf...

520 4.0

USB3.1 PHY With sophisticated architecture and advanced technology, KNiulink USB3.1 transceiver IP with PMA and PCS layer is designed for low power and high perf...

521 6.0

RapidIO PHY RapidIO is a high performance, low pin count, packet switched, full duplex, system level interconnect architecture. The architecture addresses the nee...

522 5.0

SATA/SAS 3.0 PHY With sophisticated architecture and advanced technology, KNiulink SATA/SAS transceiver IP with PMA and PCS layer is designed for low power and high pe...

523 3.0

MIPI PHY This MIPI D-PHY IP is designed to compliant with the MIPI D-PHY v1.2 specifications. It is designed for low power and high-performance application. Th...

524 2.0

MIPI D-PHY UMC 65LL Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...

525 0.0

Chiplet Solution Based on the traditional advantages of SerDes and DDR IP, KNiulink Semiconductor has launched a solution that meets the UCIe standard based on local r...

526 0.6098

MIPI D-PHY TRx 5nm The MIPI D-PHY IP is a hardmacro PHY for CSI RX or DSI TX. IO pads and ESD structures are included. Extensive built-in self test features such as loop...

527 0.0

eDisplayPort v1.4 Receiver Controller IP Core This eDisplayPort 1.4 Rx Controller IP Core is a versatile and comprehensive solution designed for easy integration into any SoC or FPGA development. ...

528 1.0

eUSB2 PHY The industry’s most advanced process nodes do not support 3.3V signaling and 5V tolerance as required by the USB 2.0 specification. 3.3V signaling was...

529 0.0

PCIe 6.0 Controller EP/RP/DM/SW with AMBA bridge & HPC features, including Arm Confidential Compute Architecture The configurable and scalable Synopsys Controller IP for PCI Express® (PCIe®) 6.0 supports all required features of the PCI Express 6.0 specification...

530 40.0

MIPI C-PHY/D-PHY Combo CSI-2 TX (Transmitter) in TSMC 40ULP The MXL-CDPHY-CSI-2-TX-T-40ULP is a high-frequency, low-power, low-cost, source-synchronous, physical layer supporting the MIPI Alliance Specification...

531 0.0

Low Power Dual PHY for UCIe low cost robust Chiplets YorChip UniPHY™ Dual PHY is a flexible version of YorChip’s multi-protocol PHY which supports UCIe and BOW standards. The Dual PHY’s unique feature ...

532 0.0

PCIe 6.0 PHY for TSMC N3P The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 6.0 meets today’s demands for higher bandwidth and power efficiency across network interfac...

533 0.0

AXI Multilayer Interconnect The AXI-MLIC is an AMBA® AXI bus interconnect fabric connecting an arbitrary number of bus masters to an arbitrary number of slaves. The AXI fabric ...

534 5.0

MIPI Compliant D-PHY TSMC 65LP Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...

535 2.0

MIPI D-PHY Global Foundries 65LPe Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...

536 3.0

MIPI D-PHY NEC 90nm Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...

537 3.0

MIPI M-PHY Designed For GF 28nm ACS-AIP-MPHY-28HK MIPI Specification Version 3.0 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabilities. A ...

538 0.0

MIPI M-PHY Designed For TSMC 28nm ACS-AIP-MPHY-28HPM MIPI Specification Version 3.0 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabilities. A...

539 25.0

MIPI D-PHY V1.2@2.5GHz TSMC28nm HPC+ Arasan has the industry’s broadest portfolio of foundry and process technology support for MIPI D-PHY in the industry. The MIPI D-PHY analog IP is ava...

540 1.0

USB 2.0 On-The-Go Controller The Arasan USB 2.0 OTG IP Core is compliant with the OTG Supplement Rev. 1.0a. The USB 2.0 OTG core supports both Host Controller, Device Controller a...

541 1.0

USB 2.0 PHY For On-The-Go Controller The Arasan ACS-AIP-USB2 USB 2.0 PHY IP core is a Transceiver compliant with the USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) level 3 specific...

542 0.0

USB 3.0 Device Upgrade IP Core The USB 3.0 Device Upgrade IP enables designers in the PC, mobile, consumer and communication markets to bring significant power and performance enhan...

543 1.0

MIPI SoundWire Master Controller 1.1 The Total MIPI Soundwire IP Solution enables early adopters the fastest path to adoption of this new standard by offering a comprehensive IP package t...

544 0.0

AXI to APB Bridge The AXI2APB implements a bridge between AXI and APB buses, allowing the connection of peripherals with an APB interface to an AXI bus. The highly con...

545 1.0

MIPI SoundWire Slave Controller 1.1 The Total MIPI Soundwire IP Solution enables early adopters the fastest path to adoption of this new standard by offering a comprehensive IP package t...

546 25.0

MIPI C-PHY-D-PHY Combo PHY IP on TSMC 28nm HPC+ Combination MIPI CPHY-DPHY Analog Interface The MIPI C-PHY V1.0 improves throughput over a bandwidth limited channel, allowing more data without in...

547 25.0

MIPI C-PHY v1.1 Combination MIPI CPHY-DPHY Analog Interface The MIPI C-PHY V1.0 improves throughput over a bandwidth limited channel, allowing more data without in...

548 1.0

USB 2.0 PHY TSMC 40LP The Arasan USB 2.0 PHY IP core is a transceiver compliant with the USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) level 3 specification, for use...

549 0.0

USB 2.0 PHY TSMC 40G The Arasan USB 2.0 PHY IP core is a transceiver compliant with the USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) level 3 specification, for use...

550 1.0

USB 2.0 PHY SMIC 130 The Arasan USB 2.0 PHY IP core is a transceiver compliant with the USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) level 3 specification, for use...