601 0.0

MIPI D-PHY Universal IP in TSMC 28HPM The MXL-DPHY-UNIV-T-28HPM is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-...

602 0.0

MIPI D-PHY Universal IP in SMIC 130nm The MXL-DPHY-UNIVERSAL-S-130 is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for...

603 0.0

MIPI D-PHY DSI RX (Receiver) in TSMC 110G The MXL-DPHY-DSI-RX-T-110G is a high-frequency, low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for ...

604 0.0

MIPI D-PHY DSI TX (Transmitter) in TSMC 65LP The MXL-DPHY-DSI-TX-T-65LP is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D...

605 0.0

MIPI D-PHY CSI-2 RX (Receiver) in TSMC 40LP The MXL-DPHY-CSI-2-RX-T-40LP is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for...

606 0.0

MIPI D-PHY CSI-2 TX (Transmitter) in TSMC 40LP The MXL-DPHY-CSI-2-TX-T-40LP is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for...

607 10.0

USB 2.0 picoPHY in UMC (40nm, 28nm) The Synopsys USB 2.0 picoPHY provides designers with a complete physical (PHY) layer IP solution, designed for low power mobile and consumer applicati...

608 0.0

MIPI M-PHY in SMIC 130nm The MXL-MPHY-S-130 is a high-frequency low-power, low-cost, Physical Layer IP compliant with the MIPI Alliance Standard for M-PHY. The IP can be used...

609 5.0

USB Power Delivery 3.1 Physical Layer CT20602 is a complete USB Power Delivery 3.1 Physical Layer. It also implements that part of the USB Power Delivery 3.1 Protocol Layer which are def...

610 5.0

SOF-Calibrated 48MHz USB Clock CT20101 extracts a precise 48MHz clock frequency underlying a USB 1.1 data stream. The device implements a loop that controls the output frequency o...

611 5.0

Low/Full Speed USB Billboard Controller The CT25100 is a Full-Speed USB controller, which enumerates as Billboard Device. It integrates all necessary infrastructures, including the CT201...

612 0.0

Ultra Low-Latency IP PCI-express Framework LeWiz makes available its low-latency PCI-express framework for IP licensing - targeting low-latency applications such as those in the financial secto...

613 11.0

MIPI D-PHY ...

614 0.0

MIPI C-PHY/D-PHY Combo CSI-2 TX 3.5Gsps/trio in TSMC 28nm The MXL-CDPHY-3p5G-CSI-2-TX-T-28HPC+ is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specifi...

615 0.0

eDisplay Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 22ULP eDP/DP Tx PHY is designed for chips that perform eDP/DP data communication while operating at low power consumption. The main link is a multi-gigabit ...

616 0.0

MIPI D-PHY Universal IP in TSMC 40LP for Automotive The MXL-DPHY-UNIVERSAL-T-40LP is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard fo...

617 0.0

224G Ethernet PHY IP for TSMC N3P The Synopsys 224G Ethernet PHY IP, an integral part of Synopsys’ high-speed SerDes IP portfolio, meets the growing high bandwidth and low latency need...

618 8.5077

PCIe 4.0 PHY (5nm) The PCIe PHY IP consists of hardmacro PMA and softmacro PCS compliant to PCIe Base 4.0 specification. This IP offers a cost-effective and low-power so...

619 5.0

MIPI C-PHY v2.0 /D-PHY v2.5 Combo IP MIPI D-PHY is a serial interface technology which is widely adopted in smartphones and other multimedia enabled mobile devices. To further improve thr...

620 0.0

MIPI C/D PHY TX This MIPI C-PHY & D-PHY combo IP is designed to compliant with the MIPI C-PHY v1.0 & D-PHY v1.2 specifications. It is designed for low power and high-...

621 0.0

MIPI C-PHY/D-PHY Combo CSI-2 TX 4.5Gsps/trio in TSMC 28nm The MXL-CDPHY-4p5G-CSI-2-TX-T-28HPC+ is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specifi...

622 0.0

MIPI D-PHY DSI RX (Receiver) in TSMC 65LP The MXL-DPHY-DSI-RX-T-65LP is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D...

623 45.0

32G Multi Rate Very Short Reach SerDes PHY - GlobalFoundries 12LP and 12LPP Extoll’s SerDes architecture is based on digital design elements and methodologies. Plain analog blocks are only used where absolutely necessary. Vari...

624 45.0

32G Multi Rate Long Reach SerDes PHY - GlobalFoundries 12LP and 12LPP Extoll’s SerDes architecture is based on digital design elements and methodologies. Plain analog blocks are only used where absolutely necessary. Vari...

625 0.0

MIPI DPHY RX This MIPI D-PHY IP is designed to compliant with the MIPI D-PHY v1.2 specifications. It is designed for low power and high-performance application. Th...

626 0.0

Single Carrier Modem The designed Single Carrier is working at adjustable sampling rate as low as 83.457 KHz, as high as 56 MHz and it supports adjustable band width as lo...

627 8.5077

PCIe 4.0 PHY (8nm) The PCIe PHY IP consists of hardmacro PMA and softmacro PCS compliant to PCIe Base 4.0 specification. This IP offers a cost-effective and low-power so...

628 0.0

MIPI D-PHY DSI TX (Transmitter) in TSMC 28nm The MXL-D-PHY-DSI-TX-T-28HPC+ is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification ...

629 6.5077

MIPI C-PHY TRx 2.5Gsps) / D-PHY TRx 4.5Gbps Combo PHY (8nm) The MIPI D-PHY/C-PHY Combo IP supports data rates of up to 4.5Gbps for D-PHY and 2.5Gsps for C-PHY. It operates in High-Speed (HS), Low-Power (LP), an...

630 0.0

PHY IP for PCIe 6.0 on TSMC N5 The multi-channel Synopsys PHY IP for PCI Express (PCIe) 6.0 meets today’s demands for higher bandwidth and power efficiency across network interface ...

631 0.0

MIPI D-PHY CSI-2 TX (Transmitter) IP in TSMC 40ULP The MXL-DPHY-CSI-2-TX-T-40ULP is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification ...

632 0.0

MIPI D-PHY DSI RX (Receiver) in DBHitek 180nm The MXL-DPHY-DSI-RX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY. ...

633 5.0

I2C Master Serial Interface Controller The CC-I2C_MST-APB is a synthesisable Verilog model of a I2C serial interface controller. The I2C core can be efficiently implemented on FPGA and ASIC...

634 5.0

SPI Serial Peripheral Interface Master/Slave The CC-SPI-APB is a synthesisable Verilog model of a SPI serial peripheral interface Master/Slave controller. The SPI core can be efficiently implemen...

635 5.0

I2C Master Serial Interface Controller The CC-I2C_MST-AXI is a synthesisable Verilog model of a I2C serial interface controller. The I2C core can be efficiently implemented on FPGA and ASIC...

636 5.0

UART Serial Interface Controller The CC-UART-APB is a synthesisable Verilog model of a UART serial interface controller. The UART core can be efficiently implemented on FPGA and ASIC ...

637 5.0

Peripheral Direct Memory Access Controller The CC-PDMA-APB-AHB is a synthesisable Verilog model of a peripheral direct memory access controller. The PDMA core can be efficiently implemented on ...

638 5.0

Peripheral Direct Memory Access Controller The CC-PDMA-AXI-AXI is a synthesisable Verilog model of a peripheral direct memory access controller. The PDMA core can be efficiently implemented on ...

639 5.0

Configurable Timer Counter The CC-TIMER-APB is a synthesisable Verilog model timer counter controller. The TIMER core can be efficiently implemented on FPGA and ASIC technologie...

640 5.0

Configurable System Tick Counter The CC-SYSTICK-APB is a synthesisable Verilog model of a system tick timer counter controller. The SYSTICK core can be efficiently implemented on FPGA...

641 5.0

Configurable Watchdog Timer The CC-WDT-APB is a synthesisable Verilog model of a watchdog timer controller. The WDT core can be efficiently implemented on FPGA and ASIC technolog...

642 5.0

General Purpose Input/Output Controller The CC-GPIO-APB is a synthesisable Verilog model of a General Purpose Input/Output Controller. The GPIO core can be efficiently implemented on FPGA an...

643 0.0

MIPI D-PHY CSI-2 RX+ (Receiver) IP in TSMC 28HPM The MXL-DPHY-CSI-2-RX+-T-28HPM is a high frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard f...

644 5.0

General Purpose Input/Output Controller The CC-GPIO-AXI is a synthesisable Verilog model of a General Purpose Input/Output Controller. The GPIO core can be efficiently implemented on FPGA an...

645 5.0

Advanced Encryption Standard Module The CC-AES-APB is a synthesisable Verilog model of a Advanced Encryption Standard module. The AES core can be efficiently implemented on FPGA and ASIC...

646 0.0

MIPI M-PHY Gear 5 for TSMC N3E The silicon-proven Synopsys MIPI® M-PHY IP, compliant with the latest MIPI M-PHY v4.1 specification, supports multiple gears and a broad range of high...

647 0.0

PCIe 5.0 IP on Samsung SF5 The multi-channel DesignWare® PHY IP for PCI Express® (PCIe®) 5.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s demands ...

648 11.0

MIPI C-PHY/D-PHY Combo CSI-2 TX+ IP 3.5Gsps/2.5Gbps The MXL-CD-PHY-CSITX+-ST-28FDSOI is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specificati...

649 0.0

MIPI D-PHY DSI RX (Receiver) in TSMC 40LP The MXL-DPHY-DSI-RX-T-40LP is a high- frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Standard for D-PH...

650 0.0

Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 12FFC The DisplayPort v1.4 Tx PHY IP in 12FFC is a modernistic technology designed to be integrated into chip designs for various devices, including graphic...