651 0.0

PHY IP for PCIe 6.0 on TSMC N5 The multi-channel Synopsys PHY IP for PCI Express (PCIe) 6.0 meets today’s demands for higher bandwidth and power efficiency across network interface ...

652 0.0

MIPI D-PHY CSI-2 TX (Transmitter) IP in TSMC 40ULP The MXL-DPHY-CSI-2-TX-T-40ULP is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification ...

653 0.0

UCIe PHY on TSMC N3E Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netwo...

654 0.0

MIPI D-PHY DSI RX (Receiver) in Dongbu 180nm The MXL-DPHY-DSI-RX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY. ...

655 5.0

I2C Master Serial Interface Controller The CC-I2C_MST-APB is a synthesisable Verilog model of a I2C serial interface controller. The I2C core can be efficiently implemented on FPGA and ASIC...

656 5.0

SPI Serial Peripheral Interface Master/Slave The CC-SPI-APB is a synthesisable Verilog model of a SPI serial peripheral interface Master/Slave controller. The SPI core can be efficiently implemen...

657 5.0

I2C Master Serial Interface Controller The CC-I2C_MST-AXI is a synthesisable Verilog model of a I2C serial interface controller. The I2C core can be efficiently implemented on FPGA and ASIC...

658 5.0

UART Serial Interface Controller The CC-UART-APB is a synthesisable Verilog model of a UART serial interface controller. The UART core can be efficiently implemented on FPGA and ASIC ...

659 5.0

Peripheral Direct Memory Access Controller The CC-PDMA-APB-AHB is a synthesisable Verilog model of a peripheral direct memory access controller. The PDMA core can be efficiently implemented on ...

660 5.0

Peripheral Direct Memory Access Controller The CC-PDMA-AXI-AXI is a synthesisable Verilog model of a peripheral direct memory access controller. The PDMA core can be efficiently implemented on ...

661 5.0

Configurable Timer Counter The CC-TIMER-APB is a synthesisable Verilog model timer counter controller. The TIMER core can be efficiently implemented on FPGA and ASIC technologie...

662 5.0

Configurable System Tick Counter The CC-SYSTICK-APB is a synthesisable Verilog model of a system tick timer counter controller. The SYSTICK core can be efficiently implemented on FPGA...

663 5.0

Configurable Watchdog Timer The CC-WDT-APB is a synthesisable Verilog model of a watchdog timer controller. The WDT core can be efficiently implemented on FPGA and ASIC technolog...

664 5.0

General Purpose Input/Output Controller The CC-GPIO-APB is a synthesisable Verilog model of a General Purpose Input/Output Controller. The GPIO core can be efficiently implemented on FPGA an...

665 0.0

MIPI D-PHY CSI-2 RX+ (Receiver) IP in TSMC 28HPM The MXL-DPHY-CSI-2-RX+-T-28HPM is a high frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard f...

666 5.0

General Purpose Input/Output Controller The CC-GPIO-AXI is a synthesisable Verilog model of a General Purpose Input/Output Controller. The GPIO core can be efficiently implemented on FPGA an...

667 5.0

Advanced Encryption Standard Module The CC-AES-APB is a synthesisable Verilog model of a Advanced Encryption Standard module. The AES core can be efficiently implemented on FPGA and ASIC...

668 0.0

MIPI M-PHY Gear 5 for TSMC N3E The silicon-proven Synopsys MIPI® M-PHY IP, compliant with the latest MIPI M-PHY v4.1 specification, supports multiple gears and a broad range of high...

669 0.0

PCIe 5.0 IP on Samsung SF5 The multi-channel DesignWare® PHY IP for PCI Express® (PCIe®) 5.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s demands ...

670 11.0

MIPI C-PHY/D-PHY Combo CSI-2 TX+ IP 3.5Gsps/2.5Gbps The MXL-CD-PHY-CSITX+-ST-28FDSOI is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specificati...

671 0.0

MIPI D-PHY DSI RX (Receiver) in TSMC 40LP The MXL-DPHY-DSI-RX-T-40LP is a high- frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Standard for D-PH...

672 60.0

Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 12FFC The DisplayPort v1.4 Tx PHY IP in 12FFC is a modernistic technology designed to be integrated into chip designs for various devices, including graphic...

673 0.0

USB 3.0/ PCIe 3.0/ SATA 3.0 Combo PHY IP, Silicon Proven in SAM 8LPP The unified PHY complies with the USB, USB 3.0, Serial ATA, Peripheral Component Interconnect Express (PCIe), and USB 2.0 interface protocols (USB Hig...

674 0.0

LVDS Tx IP, Silicon Proven SMIC 14SF+ The Low-Voltage Differential Signaling Transmitter IP Core provides a very High speed and Low power differential data transfer for Video interface and...

675 0.0

PCIe 3.0 Serdes PHY IP, Silicon Proven in SMIC 28SF This Peripheral Component Interconnect Express (PCIe) x4 PHY is compliant with PCIe 3.0 Base Specification with support of PIPE 4.3 interface spec. Lo...

676 0.0

PCIe 2.0 Serdes PHY IP, Silicon Proven in SMIC 28HKMG A physical layer (PHY) IP solution for consumer electronics, the PCIe Gen 2 PHY IP allows for customization. The PHY IP complies with the PCIe2.0 fund...

677 0.0

12G Multiprotocol Serdes IP, Silicon Proven in SMIC 14SF+ The multi-protocol SerDes PHY consist of Peripheral Component Interconnect Express (PCIe) compliant with PCIe 2.0 Base Specification with support of P...

678 0.0

MIPI D-PHY Tx IP, Silicon Proven in TSMC 28HPC+ The MIPI D-PHY Tx IP Core fully complies with version 1.2 of the D-PHY specification. It supports the Display Serial Interface and the MIPI Camera Ser...

679 0.0

MIPI D-PHY DSI RX (Receiver) in SMIC 130nm The MXL-DPHY-DSI-RX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Standard for D-PHY. The...

680 50.0

MIPI D-PHY Rx IP, Silicon Proven in TSMC 28HPC+ The MIPI D-PHY Rx IP Core in 28HPC+ aligns precisely with the D-PHY specification version 1.2, facilitating support for the Display Serial Interface (...

681 0.0

USB 2.0 PHY IP, Silicon Proven in SMIC 12SF++ A full physical layer (PHY) IP solution designed for outstanding performance and minimal power consumption is the USB2.0 PHY IP. The USB2.0 IP impleme...

682 50.0

USB 2.0 PHY IP, Silicon Proven in TSMC 22ULP The USB 2.0 PHY IP Core is a full physical layer (PHY) IP solution created for excellent performance and low power consumption. The High-Speed USB 2.0...

683 0.0

eDisplayPort v1.4 Transmitter Controller IP Core This eDisplayPort 1.4 Tx Controller IP Core integrates into any SoC or FPGA development, supporting the eDisplayPort 1.4b specification. It can be imp...

684 0.0

USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in SMIC 55LL The combined PHY complies with the Peripheral Component Interconnect Express (PCIe), Serial ATA, USB, USB 3.0, and USB 2.0 interface protocols (USB Hi...

685 0.0

USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in SMIC 28SF The combined PHY complies with USB (USB 3.0, USB 2.0), PCIe (Peripheral Component Interconnect Express), Serial ATA (SATA 3.0 Specification), and PIPE...

686 0.0

USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in SMIC 12SF++ Serial ATA (SATA) compliant with SATA 3.0 Specification, Peripheral Component Interconnect Express (PCIe) compliant with PIPE interface protocol, and ...

687 0.0

USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in UMC 55SP/EF The combination PHY consists of a Serial ATA (SATA) conforming with the SATA 3.0 Specification, a Peripheral Component Interconnect Express (PCIe) com...

688 0.0

USB 3.1 Type-C PHY IP, Silicon Proven in SMIC 14SF+ The USB3.1Type-C PHY is a high-performance, high-speed SERDES IP designed for semiconductors that support low-power, high-bandwidth data transfers. Th...

689 0.0

USB 3.1 Type-C PHY IP, Silicon Proven in SMIC 12SF++ A high performance, high-speed SERDES IP known as USB3.1Type-C PHY was created for semiconductors that allow high bandwidth data transfers while using...

690 0.0

MIPI D-PHY CSI-2 RX (Receiver) in TSMC 65LP The MXL-DPHY-CSI-2-RX-T-65LP is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Standard for D-P...

691 0.0

USB 3.1 Type-C PHY IP, Silicon Proven in TSMC 55ULP USB3.1Type-C PHY IP is a high performance high speed SERDES IP designed for chips that perform high bandwidth data communication while operating at lo...

692 0.0

PCIe 3.0 Serdes PHY IP, Silicon Proven in SMIC 12SF+/SF++ This Peripheral Component Interconnect Express (PCIe) x4 PHY is compliant with PCIe 3.0 Base Specification with support of PIPE 4.3 interface spec. Lo...

693 0.0

PCIe 3.0 Serdes PHY IP, Silicon Proven in GF 22FDX This PCIe 3.0 PHY complies with the PCIe 3.0 Base Specification and supports the PIPE 4.3 interface specification. The Gen 3 has a capability for extr...

694 0.0

12.5G Multiprotocol Serdes IP, Silicon Proven in SMIC 12SF++ The multi-protocol SerDes PHY includes Peripheral Component Interconnect Express (PCIe) conforming with PCIe 2.0 Base Specification with support for P...

695 0.0

12.5G Multiprotocol Serdes IP, Silicon Proven in UMC 28HPC The multi-protocol SerDes PHY consists of Serial ATA (SATA) conforming with SATA 3.0 Specification, Peripheral Component Interconnect Express (PCIe) c...

696 0.0

V-by-One/ LVDS Tx IP, Silicon Proven in SMIC 40LL The V-by-One® HS technology aims to transmit video signals at a high data rate using internal equipment connections. The requirements to create a tran...

697 0.0

V-by-One/LVDS Rx IP, Silicon Proven in SMIC 40LL V-by-One® HS technology targets a high-speed data transmission of video signals based on internal connection of equipment. V-by-One® HS Standard defin...

698 0.0

PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 16FFC For high-bandwidth applications, the PCIe 5.0 PHY IP offers excellent performance, multi-lane capabilities, and low power design. The PCIe 5.0 IP comp...

699 0.0

PCIe 4.0 Serdes PHY IP Silicon Proven in TSMC 7nm The high-bandwidth applications benefit from the low power, multi-lane, and high-performance PCIe 4.0 PHY IP's design. A full variety of PCIe 4.0 Base...

700 0.0

PCIe 4.0 Serdes PHY IP, Silicon Proven in TSMC 16FFC For high-bandwidth applications, the PCIe 4.0 PHY IP delivers high-performance, multi-lane capabilities and a low-power design. A full variety of PCIe...