651 20.0

MIPI C-PHY v2.0 /D-PHY v2.5 Combo IP MIPI D-PHY is a serial interface technology which is widely adopted in smartphones and other multimedia enabled mobile devices. To further improve thr...

652 50.0

40G UCIe PHY for organic substrate standard packages Synopsys UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale data center, AI,...

653 50.0

40G UCIe PHY for high-density advanced packages Synopsys UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale data center, AI,...

654 18.0

Analog I/O - low capacitance, low leakage Analog I/OS and power line ESD solutions All voltage domains (0.75V to 5V) Additional voltage (e.g. 12V in 28nm proven) Ultra-low leakage Low para...

655 0.0

MIPI C/D PHY TX This MIPI C-PHY & D-PHY combo IP is designed to compliant with the MIPI C-PHY v1.0 & D-PHY v1.2 specifications. It is designed for low power and high-...

656 51.0

MIPI C-PHY/D-PHY Combo CSI-2 TX 4.5Gsps/trio in TSMC 28nm The MXL-CDPHY-4p5G-CSI-2-TX-T-28HPC+ is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specifi...

657 0.0

MIPI D-PHY DSI RX (Receiver) in TSMC 65LP The MXL-DPHY-DSI-RX-T-065LP is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for ...

658 45.0

32G Multi Rate Very Short Reach SerDes PHY - GlobalFoundries 12LP and 12LPP Extoll’s SerDes architecture is based on digital design elements and methodologies. Plain analog blocks are only used where absolutely necessary. Vari...

659 45.0

32G Multi Rate Long Reach SerDes PHY - GlobalFoundries 12LP and 12LPP Extoll’s SerDes architecture is based on digital design elements and methodologies. Plain analog blocks are only used where absolutely necessary. Vari...

660 0.0

MIPI DPHY RX This MIPI D-PHY IP is designed to compliant with the MIPI D-PHY v1.2 specifications. It is designed for low power and high-performance application. Th...

661 0.0

Single Carrier Modem The designed Single Carrier is working at adjustable sampling rate as low as 83.457 KHz, as high as 56 MHz and it supports adjustable band width as lo...

662 3.0

PCIe 4.0 PHY (8nm) The PCIe PHY IP consists of hardmacro PMA and softmacro PCS compliant to PCIe Base 4.0 specification. This IP offers a cost-effective and low-power so...

663 0.0

MIPI D-PHY DSI TX (Transmitter) in TSMC 28nm The MXL-D-PHY-DSI-TX-T-28HPC+ is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification ...

664 3.0

MIPI C-PHY TRx 2.5Gsps) / D-PHY TRx 4.5Gbps Combo PHY (8nm) The MIPI D-PHY/C-PHY Combo IP supports data rates of up to 4.5Gbps for D-PHY and 2.5Gsps for C-PHY. It operates in High-Speed (HS), Low-Power (LP), an...

665 0.0

PHY IP for PCIe 6.0 on TSMC N5 The multi-channel Synopsys PHY IP for PCI Express (PCIe) 6.0 meets today’s demands for higher bandwidth and power efficiency across network interface ...

666 1.0

MIPI D-PHY CSI-2 TX (Transmitter) IP in TSMC 40ULP The MXL-DPHY-CSI-2-TX-T-40ULP is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification ...

667 0.0

UCIe PHY on TSMC N3E Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netwo...

668 0.0

MIPI D-PHY DSI RX (Receiver) in Dongbu 180nm The MXL-DPHY-DSI-RX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY. ...

669 5.0

I2C Master Serial Interface Controller The CC-I2C_MST-APB is a synthesisable Verilog model of a I2C serial interface controller. The I2C core can be efficiently implemented on FPGA and ASIC...

670 5.0

SPI Serial Peripheral Interface Master/Slave The CC-SPI-APB is a synthesisable Verilog model of a SPI serial peripheral interface Master/Slave controller. The SPI core can be efficiently implemen...

671 5.0

I2C Master Serial Interface Controller The CC-I2C_MST-AXI is a synthesisable Verilog model of a I2C serial interface controller. The I2C core can be efficiently implemented on FPGA and ASIC...

672 5.0

UART Serial Interface Controller The CC-UART-APB is a synthesisable Verilog model of a UART serial interface controller. The UART core can be efficiently implemented on FPGA and ASIC ...

673 5.0

Peripheral Direct Memory Access Controller The CC-PDMA-APB-AHB is a synthesisable Verilog model of a peripheral direct memory access controller. The PDMA core can be efficiently implemented on ...

674 5.0

Peripheral Direct Memory Access Controller The CC-PDMA-AXI-AXI is a synthesisable Verilog model of a peripheral direct memory access controller. The PDMA core can be efficiently implemented on ...

675 5.0

Configurable Timer Counter The CC-TIMER-APB is a synthesisable Verilog model timer counter controller. The TIMER core can be efficiently implemented on FPGA and ASIC technologie...

676 5.0

Configurable System Tick Counter The CC-SYSTICK-APB is a synthesisable Verilog model of a system tick timer counter controller. The SYSTICK core can be efficiently implemented on FPGA...

677 5.0

Configurable Watchdog Timer The CC-WDT-APB is a synthesisable Verilog model of a watchdog timer controller. The WDT core can be efficiently implemented on FPGA and ASIC technolog...

678 5.0

General Purpose Input/Output Controller The CC-GPIO-APB is a synthesisable Verilog model of a General Purpose Input/Output Controller. The GPIO core can be efficiently implemented on FPGA an...

679 30.0

MIPI D-PHY CSI-2 RX+ (Receiver) IP in TSMC 28HPM The MXL-DPHY-CSI-2-RX+ is a high frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY...

680 5.0

General Purpose Input/Output Controller The CC-GPIO-AXI is a synthesisable Verilog model of a General Purpose Input/Output Controller. The GPIO core can be efficiently implemented on FPGA an...

681 5.0

Advanced Encryption Standard Module The CC-AES-APB is a synthesisable Verilog model of a Advanced Encryption Standard module. The AES core can be efficiently implemented on FPGA and ASIC...

682 0.0

MIPI M-PHY Gear 5 for TSMC N3E The silicon-proven Synopsys MIPI® M-PHY IP, compliant with the latest MIPI M-PHY v4.1 specification, supports multiple gears and a broad range of high...

683 0.0

PCIe 5.0 IP on Samsung SF5 The multi-channel DesignWare® PHY IP for PCI Express® (PCIe®) 5.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s demands ...

684 25.0

MIPI C-PHY/D-PHY Combo CSI-2 TX+ IP 3.5Gsps/2.5Gbps The MXL-CD-PHY-CSITX+-ST-28FDSOI is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specificati...

685 0.0

MIPI D-PHY DSI RX (Receiver) in TSMC 40LP The MXL-DPHY-DSI-RX is a high- frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Standard for D-PHY. The...

686 100.0

Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 12FFC The DisplayPort v1.4 Tx PHY IP in 12FFC is a modernistic technology designed to be integrated into chip designs for various devices, including graphic...

687 0.0

USB 3.0/ PCIe 3.0/ SATA 3.0 Combo PHY IP, Silicon Proven in SAM 8LPP The unified PHY complies with the USB, USB 3.0, Serial ATA, Peripheral Component Interconnect Express (PCIe), and USB 2.0 interface protocols (USB Hig...

688 0.0

LVDS Tx IP, Silicon Proven SMIC 14SF+ The Low-Voltage Differential Signaling Transmitter IP Core provides a very High speed and Low power differential data transfer for Video interface and...

689 0.0

PCIe 3.0 Serdes PHY IP, Silicon Proven in SMIC 28SF This Peripheral Component Interconnect Express (PCIe) x4 PHY is compliant with PCIe 3.0 Base Specification with support of PIPE 4.3 interface spec. Lo...

690 0.0

PCIe 2.0 Serdes PHY IP, Silicon Proven in SMIC 28HKMG A physical layer (PHY) IP solution for consumer electronics, the PCIe Gen 2 PHY IP allows for customization. The PHY IP complies with the PCIe2.0 fund...

691 0.0

12G Multiprotocol Serdes IP, Silicon Proven in SMIC 14SF+ The multi-protocol SerDes PHY consist of Peripheral Component Interconnect Express (PCIe) compliant with PCIe 2.0 Base Specification with support of P...

692 0.0

MIPI D-PHY Tx IP, Silicon Proven in TSMC 28HPC+ The MIPI D-PHY Tx IP Core fully complies with version 1.2 of the D-PHY specification. It supports the Display Serial Interface and the MIPI Camera Ser...

693 0.0

MIPI D-PHY DSI RX (Receiver) in SMIC 130nm The MXL-DPHY-DSI-RX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Standard for D-PHY. The...

694 50.0

MIPI D-PHY Rx IP, Silicon Proven in TSMC 28HPC+ The MIPI D-PHY Rx IP Core in 28HPC+ aligns precisely with the D-PHY specification version 1.2, facilitating support for the Display Serial Interface (...

695 0.0

USB 2.0 PHY IP, Silicon Proven in SMIC 12SF++ A full physical layer (PHY) IP solution designed for outstanding performance and minimal power consumption is the USB2.0 PHY IP. The USB2.0 IP impleme...

696 50.0

USB 2.0 PHY IP, Silicon Proven in TSMC 22ULP The USB 2.0 PHY IP Core is a full physical layer (PHY) IP solution created for excellent performance and low power consumption. The High-Speed USB 2.0...

697 0.0

eDisplayPort v1.4 Transmitter Controller IP Core This eDisplayPort 1.4 Tx Controller IP Core integrates into any SoC or FPGA development, supporting the eDisplayPort 1.4b specification. It can be imp...

698 0.0

USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in SMIC 55LL The combined PHY complies with the Peripheral Component Interconnect Express (PCIe), Serial ATA, USB, USB 3.0, and USB 2.0 interface protocols (USB Hi...

699 0.0

USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in SMIC 28SF The combined PHY complies with USB (USB 3.0, USB 2.0), PCIe (Peripheral Component Interconnect Express), Serial ATA (SATA 3.0 Specification), and PIPE...

700 0.0

USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in SMIC 12SF++ Serial ATA (SATA) compliant with SATA 3.0 Specification, Peripheral Component Interconnect Express (PCIe) compliant with PIPE interface protocol, and ...