801 0.0

MIPI D-PHY Universal IP in TSMC 16FFC for Automotive The MXL-DPHY-UNIV-T-16FFC is a high-frequency low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for D...

802 0.0

PCIe 4.0 PHY IP for SS 14LPU The multi-channel Synopsys PHY IP for PCI Express® 4.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ deman...

803 0.0

224G-LR SerDes PHY for UALink for Intel 18A 224G-LR SerDes PHY enables 1.6T and 800G networks for UALink The Cadence 224G SerDes PHY for UALink enables the emerging 1.6T and 800G scale-up net...

804 0.0

224G-LR SerDes PHY for UALink for TSMC N3E/N3P 224G-LR SerDes PHY enables 1.6T and 800G networks for UALink The Cadence 224G SerDes PHY for UALink enables the emerging 1.6T and 800G scale-up netwo...

805 0.0

224G-LR SerDes PHY for TSMC N3E/N3P 224G-LR SerDes PHY enables 1.6T and 800G networks The Cadence 224G SerDes PHY for UALink enables the emerging 1.6T and 800G scale-up networks for hyp...

806 0.0

112G-ULR PAM4 SerDes PHY for TSMC N6/N7 112G-ULR Serdes PAM4 PHY Enables reliable high-speed data transfer over backplane, DAC, chip-to-chip, and chip-to-module channel The Cadence 112Gbps ...

807 0.0

112G-ULR PAM4 SerDes PHY for TSMC N5/N4P 112G-ULR Serdes PAM4 PHY Enables reliable high-speed data transfer over backplane, DAC, chip-to-chip, and chip-to-module channel The Cadence 112Gbps ...

808 0.0

112G-ULR PAM4 SerDes PHY for TSMC N3E/N3P 112G-ULR Serdes PAM4 PHY Enables reliable high-speed data transfer over backplane, DAC, chip-to-chip, and chip-to-module channel The Cadence 112Gbps ...

809 0.0

112G-ULR PAM4 SerDes PHY for Samsung SF5A 112G-ULR Serdes PAM4 PHY Enables reliable high-speed data transfer over backplane, DAC, chip-to-chip, and chip-to-module channel The Cadence 112Gbps ...

810 0.0

MIPI D-PHY CSI-2 TX (Transmitter) in TSMC 28HPC+ The MXL-DPHY-CSI-2-TX-T-28HPC+ is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Standard for D...

811 0.0

112G-VSR for TSMC N3E/N3P 112G-VSR Serdes PAM4 PHY Enables reliable high-speed data transfer over backplane, DAC, chip-to-chip, and chip-to-module channel The Cadence 112Gbps ...

812 0.0

56G-LR Pam4 SerDes for TSMC N6/N7 56G LR SerDes PHY provides exceptional performance w/ best-in-class power & area, making it ideal for machine learning and 5G The Cadence 56Gbps Long...

813 0.0

MIPI C-PHY/D-PHY Combo DSI RX (Receiver) IP in TSMC 28HPC+ The MXL-CDPHY-DSI-RX-T-28HPC+ is a high-frequency low-power, low-cost, source-synchronous, physical Layer. The PHY is configured as MIPI Slave support...

814 50.0

PHY for PCIe 5.0 and CXL for TSMC Cadence 32G NRZ multi-;protocol PHY The Cadence 32G Multi-Protocol PHY IP for TSMC is a high--performance SerDes operating from 1.25Gbps to 32Gbps ...

815 0.0

USB 2.0 PHY for Samsung 7LPP Proven PHY IP for USB Device, Host, and OTG with small footprint and low active power The ubiquity of USB 2.0 in devices makes it nearly mandatory fo...

816 0.0

28G LR Multi-Protocol SerDes (MPS) PHY Optimized for power and area, our line-up of SerDes PHYs, deliver maximum performance and flexibility for today's most challenging designs. The 28 ...

817 0.0

32G LR Multi-Protocol SerDes (MPS) PHY Designed to meet the power efficiency and performance requirements of next-generation, high-speed wireline and wireless 5G infrastructure. The 32G ...

818 0.0

16G Multi-Protocol SerDes (MPS) PHY Silicon-proven PHY for PCIe, USB, Ethernet, DisplayPort, and other protocols The 16 Gbps Multi-Protocol SerDes (MPS) PHYs are a high-performance se...

819 0.0

PCIe 4/3/2 SerDes PHY Optimized for power and area, our line-up of SerDes PHYs, deliver maximum performance and flexibility for today's most challenging applications The 1...

820 0.0

MIPI D-PHY Universal IP in TSMC 40ULP The MXL-DPHY-UNIV is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Specification for D-PHY v1....

821 0.0

PHY for PCIe 7.0 and CXL for TSMC N3E/N3P Most advanced PHY and Controller for HPC, AI/ML, Data communications, networking, and storage systems The Cadence® PHY IP for PCI Express® (PCIe®) 7....

822 0.0

PHY for PCIe 6.0 and CXL for TSMC N4P/N5P Most advanced PHY and Controller for HPC, AI/ML, Data communications, networking, and storage systems The Cadence® PHY IP for PCI Express® (PCIe®) 6....

823 25.0

PHY for PCIe 6.0 and CXL for Samsung Most advanced PHY and Controller for HPC, AI, ML, Data communications, networking, and storage systems The Cadence® PHY IP for PCI Express® (PCIe®)...

824 0.0

eUSB2V2 PHY Low voltage USB 2.0 supporting 4.8Gbps eUSB2V2 is primarily a performance enhancement to eUSB2 native mode to provide more bandwidth for peripherals,...

825 0.0

30G MR Multi-Protocol SerDes (MPS) PHY Optimized for power and area, our line-up of SerDes PHYs, deliver maximum performance and flexibility for today's most challenging designs. The 30G...

826 75.0

PCI Express (PCIe) 7.0 Controller Application-optimized, high-performance controller IP for PCIe The Cadence® Controller IP for PCIe 7.0 provides the logic required to integrate a r...

827 25.0

PCI Express (PCIe) 6.0 Controller Application-optimized, high-performance controller IP for PCIe The Cadence® Controller IP for PCIe 6.0 provides the logic required to integrate a r...

828 0.0

USB 3.x PHY for TSMC Proven PHY IP for USB Device, Host, and DRD with small footprint and low active power The ubiquity of USB 3.x in devices makes it nearly mandatory ...

829 5.0

SerDes Hard Macro-IP in GlobalFoundries 22FDX Low-power, flexible and robust Serializer-de-serializer IP built upon a proven ring-PLL based architecture, Support for multiple protocols, as well a...

830 0.0

MIPI D-PHY CSI-2 RX (Receiver) in TSMC 28HPC+ The MXL-DPHY-CSI-2-RX-T-28HPC+ is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Specification ...

831 6.0

MIPI D-PHY Receiver with PPI SP_MIPI_DPHY_RX_PPI _T28HPCP is a MIPI D-PHY Receiver, which complies with MIPI D-PHY specification version 1.2. This D-PHY design receives data from ...

832 10.0

AMBA APB Target Advanced Peripheral Bus (APB) is one of the Advanced Microcontroller Bus Architecture (AMBA) family protocols. It is a low-cost interface that is desi...

833 10.0

Wishbone Target The Wishbone System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores is a versatile design approach for semiconductor IP cores. Its go...

834 10.0

Avalon Target Avalon interfaces make system design easier by allowing you to connect components in Intel FPGAs. The Avalon interface family defines interfaces that ...

835 10.0

TileLink Target TileLink is a chip-scale connection standard that enables many masters to have synchronised memory mapped access to memory and other slave devices. Ti...

836 10.0

Bus Decoders Decoder logic controls numerous targets based on input from the initiator. It determines/decodes which target component will handle the current bus tr...

837 10.0

Bus Bridges Various bus types of protocols are available and employed in many applications, all of which require a bridge to operate safely and without loss of da...

838 10.0

Bus Convertors The bus converter module transforms 64-bit wide initiator data buses to smaller 32-bit target data buses or vice-versa. The downsizer module cuts the ...

839 10.0

Crossbars Interconnect An interconnect component connects initiators and targets in a system. A single initiator system simply requires a decoder and multiplexor, which are ...

840 0.0

MIPI C-PHY/D-PHY Combo DSI TX (Transmitter) IP in TSMC 55G The MXL-CDPHY-DSI-TX-T-55G is a high-frequency low-power, high-performance, physical Layer. The PHY is configured as a MIPI Master supporting display ...

841 1.0

USB 2.0 Device Controller The USB 2.0 Device IP core is Arasan’s latest development that enables designers in the PC, mobile, consumer and communication markets to bring signif...

842 1.0

USB 2.0 Hub Controller The Arasan USB 2.0 Hub IP core is an USB 2.0 specification compliant hub core that supports 480 Mbit/s in High Speed (HS) mode, 12 Mbit/s in Full Spe...

843 1.0

USB 2.0 EHCI Host Controller IP The Arasan USB 2.0 Host IP is an USB 2.0 specification compliant host IP core with an optional AHB, PCI, or custom host interface. The USB 2.0 Host IP...

844 0.0

I2C Host / Device Bus Controller The synchronous I2C interface is a block that interconnects an APB bus. The APB - I2C Bridge interfaces to the APB bus on the system side and the I2C ...

845 1.0

MIPI SLIMbus Host Controller v2.0 The MIPI SLIMbus Host typically resides in a mobile platform’s application processor and provides two-wire, multi-drop connectivity with multiple audi...

846 0.0

MIPI CSI-2 Receiver The Arasan CSI-2 Receiver IP Core functions as a MIPI Camera Serial Interface (CSI-2 Combo) Receiver, which interfaces between a peripheral device (Ca...

847 0.0

MIPI D-PHY Universal IP in TSMC 40LP-eF The MXL-DPHY-UNIV is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Specification for D-PHY v1....

848 20.0

MIPI CSI-2 Tansmitter v 1.3, C-PHY compatible The MIPI Camera Serial Interface (CSI-2) Transmitter, typically resides in a mobile platform’s camera module, and communicates over a D-PHY/C-PHY link...

849 1.0

MIPI SLIMbus Device Controller V2.0 The Arasan SLIMbus Device Controller IP is designed to provide MIPI SLIMbus 1.01 compliant connectivity for a peripheral device, like an audio codec, ...

850 1.0

MIPI UniPro Controller - v1.6 To address the explosive growth in the mobile industry, the Mobile Industry Processor Interface (MIPI) Alliance was created to define and promote open...