801 0.0

PCIe 6.0 PHY for TSMC N6 The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 6.0 meets today’s demands for higher bandwidth and power efficiency across network interfac...

802 1.0

32G Multi-SerDes PHY + Controller The INNOSILICON™ 32G Multi-SerDes PHY is a highly configurable IP solution capable of supporting data rates of up to 32 Gbps per lane. It is designed ...

803 0.0

MIPI C-PHY v2.0 D-PHY v2.1 for TSMC N5A Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...

804 0.0

PCIe 6.0 PHY IP for TSMC N3E The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 6.0 meets today’s demands for higher bandwidth and power efficiency across network interfac...

805 4.0

CSI2 TX; Camera Serial Interface, MIPI Compliant CSI2 – TX is part of HCL’s MIPI® compliant offerings. The CSI2 Transmitter IP supports Pixel Interface on the camera sensor side and the DPHY is suppo...

806 4.0

CSI2 RX; Camera Serial Interface, MIPI Compliant The CSI2 Receiver IP Interfaces between Camera module which has the transmitter and the application processor. The CSI2 Receiver IP is fully compliant...

807 4.0

MIL1553B IP Core MIL-STD-1553B defines specifications for terminal device operation and coupling, word structure and format, messaging protocol and electrical characte...

808 45.0

MIPI C-PHY/D-PHY Combo CSI-2 TX+ IP 4.5Gsps/4.5Gbps The MXL-CDPHY-4p5G-CSI-2-TX+-16FFC is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specifica...

809 0.0

PCIe 6.0 PHY on 5nm The PCIe PHY IP consists of hardmacro PMA and softmacro PMD compliant to PCIe Base 6.0 specification. This IP offers a cost-effective and low-power so...

810 0.0

MIPI D-PHY DSI RX (Receiver) for Automotive in GlobalFoundries 55HV The MXL-DPHY-DSI-RX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Specification for D-PHY v...

811 0.0

VESA DSC 1.2b Encoder for Xilinx FPGAs ...

812 0.0

VESA DSC 1.2b Decoder IP Core for Xilinx FPGAs ...

813 200.0

PCIe 7.0 Controller The Rambus PCI Express® (PCIe®) 7.0 Controller is a configurable and scalable design for ASIC implementations. It is backward compatible to the PCIe 6...

814 100.0

PCIe 7.0 PHY IP supporting the latest features of the evolving PCIe 7.0 specification to enable 128 GT/s and up to x16 lane configurations The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 7.0 meets today’s demands for higher bandwidth and power efficiency across backplane, and c...

815 17.0

AXI2APB Bridge Truechip's AXI2APB IP provides chip designers and architects, an efficient way to connect AXI & APB based IPs with reduced latency, power, and area....

816 0.0

16G Serdes in SMIC 28HKCP Brite Semiconductor‘s Serdes provides 2.5-32Gbps multi-rate SERDES IP which is designed for smooth integration of Multiple SERDES lanes demonstrate go...

817 0.0

2.5Gbps/lane MIPI D-PHY in SMIC 40NLL BriteSemi’s MIPI D-PHY supports speed up to 4.5Gbps per lane and an aggregate data rate of 18Gbps, which can provide high-performance MIPI D-PHY solut...

818 0.0

4.5Gbps/lane MIPI D-PHY in SMIC 28HKC+ BriteSemi’s MIPI D-PHY supports speed up to 4.5Gbps per lane and an aggregate data rate of 18Gbps, which can provide high-performance MIPI D-PHY solut...

819 0.0

PCIE4 PHY in SMIC 28HKCP Brite Semiconductor's 16Gbps PCIe PHY and controller solution provide high efficient interconnection that is optimized for PPA performance. The System...

820 0.0

MIPI D-PHY DSI RX (Receiver) in UMC 40HV The MXL-DPHY-DSI-RX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Specification for D-PHY v...

821 20.0

VESA VDC-M Decoder The Video Electronics Standards Association (VESA®) introduced the VESA Display Compression-M (VDC-M) standard, a new display interface compression st...

822 5.0

MIPI SPMI Target Controller The System Power Management Interface is a two wire interface that connects the integrated power controller (PC) of a System-on-Chip (SoC) processor s...

823 3.0

eDP v1.5a RX PHY (14nm) The eDP RX PHY supports a maximum data rate of up to HBR3 (8.1Gbps), and the general mode supports a maximum data rate of up to 4Gbps. This core IP is...

824 7.0

MIPI C-PHY 8Gsps / D-PHY 9Gbps TRX Combo PHY (2nm) The MIPI D-PHY/C-PHY Combo IP supports data rates of up to 9Gbps for D-PHY and 8Gsps for C-PHY. It operates in High-Speed (HS), Low-Power (LP), and Es...

825 3.0

MIPI D-PHY TRx 2.1Gbps (14nm) The MIPI D-PHY IP supports data rates of up to 2.1Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...

826 100.0

Multi-protocol SerDes PMA in FDSOI (GF22FDX FDX 22FDX) - PCIe1 PCIe2 PCIe3 PCIe4 and more Multiprotocol SerDes PMA supporting variety of interfaces....

827 0.0

PCIe 5.0 PHY IP for TSMC N5 The multi-channel Synopsys PHY IP for PCI Express® 5.0 and CXL includes Synopsys’ high-speed, high-performance transceiver to meet today’s application...

828 0.0

USB2.0 OTG PHY in SMIC 0.13G Brite provides USB2.0 OTG PHY which is a complete mixed-signal IP solution designed to implement OTG connectivity for a System-on-Chip (SoC) design. ...

829 0.0

USB2.0 OTG PHY in SMIC 0.13EF Brite provides USB2.0 OTG PHY which is a complete mixed-signal IP solution designed to implement OTG connectivity for a System-on-Chip (SoC) design. ...

830 0.0

MIPI D-PHY CSI-2 TX (Transmitter) in TSMC 65LP The MXL-DPHY-CSI-2-TX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Standard for D-PHY. Th...

831 0.0

USB2.0 OTG PHY in SMIC 40NEF Brite provides USB2.0 OTG PHY which is a complete mixed-signal IP solution designed to implement OTG connectivity for a System-on-Chip (SoC) design. ...

832 0.0

USB2.0 OTG PHY in SMIC 55NLL Brite provides USB2.0 OTG PHY which is a complete mixed-signal IP solution designed to implement OTG connectivity for a System-on-Chip (SoC) design. ...

833 0.0

USB2.0 OTG PHY in SMIC 55EF Brite provides USB2.0 OTG PHY which is a complete mixed-signal IP solution designed to implement OTG connectivity for a System-on-Chip (SoC) design. ...

834 0.0

USB1.1 PHY in SMIC 55PFULP Brite provides USB2.0 OTG PHY which is a complete mixed-signal IP solution designed to implement OTG connectivity for a System-on-Chip (SoC) design. ...

835 0.0

USB2.0 OTG PHY in SMIC 0.11G Brite provides USB2.0 OTG PHY which is a complete mixed-signal IP solution designed to implement OTG connectivity for a System-on-Chip (SoC) design. ...

836 0.0

USB2.0 OTG PHY in SMIC 40NLL Brite provides USB2.0 OTG PHY which is a complete mixed-signal IP solution designed to implement OTG connectivity for a System-on-Chip (SoC) design. ...

837 0.0

USB2.0 OTG PHY in SMIC 28HKC+ Brite provides USB2.0 OTG PHY which is a complete mixed-signal IP solution designed to implement OTG connectivity for a System-on-Chip (SoC) design. ...

838 0.0

USB2.0 OTG PHY in SMIC 28HKD 0.9/2.5V Brite provides USB2.0 OTG PHY which is a complete mixed-signal IP solution designed to implement OTG connectivity for a System-on-Chip (SoC) design. ...

839 0.0

USB2.0 OTG PHY in SMIC 28HKD 0.9/1.8V Brite provides USB2.0 OTG PHY which is a complete mixed-signal IP solution designed to implement OTG connectivity for a System-on-Chip (SoC) design. ...

840 0.0

MIPI C-PHY v2.0 D-PHY v2.1 RX for GF 12LP+ Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...

841 10.0

USB 3.0 femtoPHY in SMIC (28nm) The Synopsys USB-C™ 3.0 and USB 3.0 femtoPHY IP provide designers with a complete physical (PHY) layer IP solution for low-power mobile and consumer a...

842 10.0

MIPI D-PHY Universal IP in TSMC 16FFC for Automotive The MXL-DPHY-UNIV is a high-frequency low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for D-PHY v1....

843 0.0

eUSB 2.0 PHY for TSMC N3A Synopsys provides designers with silicon-proven, configurable eUSB2 PHYs that are compliant with the USB-Implementers Forum (USB-IF) eUSB2 and USB 2.0...

844 0.0

PCIe 4.0 PHY IP for SS 14LPU The multi-channel Synopsys PHY IP for PCI Express® 4.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ deman...

845 0.0

224G-LR SerDes PHY for UALink for Intel 18A 224G-LR SerDes PHY enables 1.6T and 800G networks for UALink The Cadence 224G SerDes PHY for UALink enables the emerging 1.6T and 800G scale-up net...

846 0.0

224G-LR SerDes PHY for UALink for TSMC N3E/N3P 224G-LR SerDes PHY enables 1.6T and 800G networks for UALink The Cadence 224G SerDes PHY for UALink enables the emerging 1.6T and 800G scale-up netwo...

847 0.0

224G-LR SerDes PHY for TSMC N3E/N3P 224G-LR SerDes PHY enables 1.6T and 800G networks The Cadence 224G SerDes PHY for UALink enables the emerging 1.6T and 800G scale-up networks for hyp...

848 0.0

224G-LR SerDes PHY for Rapidus 2nm 224G-LR SerDes PHY enables 1.6T and 800G networks The Cadence 224G SerDes PHY for UALink enables the emerging 1.6T and 800G scale-up networks for hyp...

849 0.0

112G-ULR PAM4 SerDes PHY for TSMC N6/N7 112G-ULR Serdes PAM4 PHY Enables reliable high-speed data transfer over backplane, DAC, chip-to-chip, and chip-to-module channel The Cadence 112Gbps ...

850 0.0

112G-ULR PAM4 SerDes PHY for TSMC N5/N4P 112G-ULR Serdes PAM4 PHY Enables reliable high-speed data transfer over backplane, DAC, chip-to-chip, and chip-to-module channel The Cadence 112Gbps ...