851 0.0

28G LR Multi-Protocol SerDes (MPS) PHY Optimized for power and area, our line-up of SerDes PHYs, deliver maximum performance and flexibility for today's most challenging applications The 2...

852 0.0

32G LR Multi-Protocol SerDes (MPS) PHY Designed to meet the power efficiency and performance requirements of next-generation, high-speed wireline and wireless 5G infrastructure The 32G MPS...

853 0.0

16G Multi-Protocol SerDes (MPS) PHY Optimized for power and area, our line-up of SerDes PHYs, deliver maximum performance and flexibility for today's most challenging applications The 1...

854 0.0

PCIe 4/3/2 SerDes PHY Optimized for power and area, our line-up of SerDes PHYs, deliver maximum performance and flexibility for today's most challenging applications The 1...

855 0.0

MIPI D-PHY Universal IP in TSMC 40ULP The MXL-DPHY-UNIV is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Specification for D-PHY v1....

856 0.0

PHY for PCIe 7.0 and CXL for TSMC N3E/N3P Most advanced PHY and Controller for HPC, AI/ML, Data communications, networking, and storage systems The Cadence® PHY IP for PCI Express® (PCIe®) 7....

857 0.0

PHY for PCIe 6.0 and CXL for TSMC N4P/N5P Most advanced PHY and Controller for HPC, AI/ML, Data communications, networking, and storage systems The Cadence® PHY IP for PCI Express® (PCIe®) 6....

858 0.0

PHY for PCIe 6.0 and CXL for Samsung Most advanced PHY and Controller for HPC, AI/ML, Data communications, networking, and storage systems The Cadence® PHY IP for PCI Express® (PCIe®) 6....

859 0.0

eUSB2V2 PHY Low voltage USB 2.0 supporting 4.8Gbps eUSB2V2 is primarily a performance enhancement to eUSB2 native mode to provide more bandwidth for peripherals,...

860 0.0

30G MR Multi-Protocol SerDes (MPS) PHY Optimized for power and area, our line-up of SerDes PHYs, deliver maximum performance and flexibility for today's most challengings applications The ...

861 0.0

PCI Express (PCIe) 7.0 Controller Application-optimized, high-performance controller IP for PCIe The Cadence® Controller IP for PCIe 7.0 provides the logic required to integrate a roo...

862 0.0

PCI Express (PCIe) 6.0 Controller Application-optimized, high-performance controller IP for PCIe The Cadence® Controller IP for PCIe 6.0 provides the logic required to integrate a roo...

863 0.0

USB 3.x PHY for TSMC Proven PHY IP for USB Device, Host, and DRD with small footprint and low active power The ubiquity of USB 3.x in devices makes it nearly mandatory fo...

864 10.0

UCIe D2D Adapter The D2D Adapter for UCIe is a scalable adapter layer between one or more protocol components and the UCIe PHY, which ensures efficient data transfer a...

865 5.0

SerDes Hard Macro-IP in GlobalFoundries 22FDX Low-power, flexible and robust Serializer-de-serializer IP built upon a proven ring-PLL based architecture, Support for multiple protocols, as well a...

866 0.0

MIPI D-PHY CSI-2 RX (Receiver) in TSMC 28HPC+ The MXL-DPHY-CSI-2-RX-T-28HPC+ is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Specification ...

867 0.0

MIPI D-PHY Receiver with PPI SP_MIPI_DPHY_RX_PPI _T28HPCP is a MIPI D-PHY Receiver, which complies with MIPI D-PHY specification version 1.2. This D-PHY design receives data from ...

868 10.0

AMBA APB Target Advanced Peripheral Bus (APB) is one of the Advanced Microcontroller Bus Architecture (AMBA) family protocols. It is a low-cost interface that is desi...

869 10.0

Wishbone Target The Wishbone System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores is a versatile design approach for semiconductor IP cores. Its go...

870 10.0

Avalon Target Avalon interfaces make system design easier by allowing you to connect components in Intel FPGAs. The Avalon interface family defines interfaces that ...

871 10.0

TileLink Target TileLink is a chip-scale connection standard that enables many masters to have synchronised memory mapped access to memory and other slave devices. Ti...

872 10.0

Bus Decoders Decoder logic controls numerous targets based on input from the initiator. It determines/decodes which target component will handle the current bus tr...

873 10.0

Bus Bridges Various bus types of protocols are available and employed in many applications, all of which require a bridge to operate safely and without loss of da...

874 10.0

Bus Convertors The bus converter module transforms 64-bit wide initiator data buses to smaller 32-bit target data buses or vice-versa. The downsizer module cuts the ...

875 10.0

Crossbars Interconnect An interconnect component connects initiators and targets in a system. A single initiator system simply requires a decoder and multiplexor, which are ...

876 0.0

MIPI C-PHY/D-PHY Combo DSI TX (Transmitter) IP in TSMC 55G The MXL-CDPHY-DSI-TX-T-55G is a high-frequency low-power, high-performance, physical Layer. The PHY is configured as a MIPI Master supporting display ...

877 1.0

USB 2.0 Device Controller The USB 2.0 Device IP core is Arasan’s latest development that enables designers in the PC, mobile, consumer and communication markets to bring signif...

878 1.0

USB 2.0 Hub Controller The Arasan USB 2.0 Hub IP core is an USB 2.0 specification compliant hub core that supports 480 Mbit/s in High Speed (HS) mode, 12 Mbit/s in Full Spe...

879 1.0

USB 2.0 EHCI Host Controller IP The Arasan USB 2.0 Host IP is an USB 2.0 specification compliant host IP core with an optional AHB, PCI, or custom host interface. The USB 2.0 Host IP...

880 0.0

I2C Host / Device Bus Controller The synchronous I2C interface is a block that interconnects an APB bus. The APB - I2C Bridge interfaces to the APB bus on the system side and the I2C ...

881 1.0

MIPI SLIMbus Host Controller v2.0 The MIPI SLIMbus Host typically resides in a mobile platform’s application processor and provides two-wire, multi-drop connectivity with multiple audi...

882 0.0

MIPI CSI-2 Receiver The Arasan CSI-2 Receiver IP Core functions as a MIPI Camera Serial Interface (CSI-2 Combo) Receiver, which interfaces between a peripheral device (Ca...

883 0.0

MIPI D-PHY Universal IP in TSMC 40LP-eF The MXL-DPHY-UNIV is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Specification for D-PHY v1....

884 20.0

MIPI CSI-2 Tansmitter v 1.3, C-PHY compatible The MIPI Camera Serial Interface (CSI-2) Transmitter, typically resides in a mobile platform’s camera module, and communicates over a D-PHY/C-PHY link...

885 1.0

MIPI SLIMbus Device Controller V2.0 The Arasan SLIMbus Device Controller IP is designed to provide MIPI SLIMbus 1.01 compliant connectivity for a peripheral device, like an audio codec, ...

886 1.0

MIPI UniPro Controller - v1.6 To address the explosive growth in the mobile industry, the Mobile Industry Processor Interface (MIPI) Alliance was created to define and promote open...

887 10.0

MIPI DSI-2 Transmit Controller v1.0 The Arasan DSI-2 Device Controller IP is designed to provide MIPI DSI-2 1.0 compliant high speed serial connectivity for mobile host processors using ...

888 1.0

PCIe 2.0 End Point IP Core - PCIe with FIFO Interface The Arasan PCI Express End Point is a high-speed, high-performance, and lowpowerIP core that is fully compliant to the PCI Express Specification 1.1 a...

889 1.0

USB 3.0 Device Controller The USB 3.0 Device IP core is Arasan’s latest development that enables designers in the PC, mobile, consumer and communication markets to bring signif...

890 1.0

MIPI HSI Controller - (High-Speed Synchronous Serial Interface) The High Speed Synchronous Serial Interface (HSI) Controller is used to provide high bandwidth, point-to-point, serial communication between two peers...

891 0.0

MIPI D-PHY Universal IP in TSMC 55LP The MXL-DPHY-UNIV is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Specification for D-PHY v1....

892 10.0

ONFI 3.2 NAND Flash Controller The Arasan ONFI 3.2 compliant NAND Flash Controller IP Core is a full featured, easy to use, synthesizable design that is easily integrated into any S...

893 1.0

USB HSIC PHY - High Speed Inter-Chip IP Core USB is the ubiquitous peripherals interconnect of choice for large number of computing and consumer applications. Many systems provide a comprehensive...

894 5.0

USB 2.0 PHY The Arasan USB 2.0 PHY IP core is a transceiver compliant with the USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) level 3 specification, for use...

895 1.0

MIPI RFFE Master Controller IP Core Mobile radio communication is trending towards complex multi-radio systems comprising of several transceivers. The MIPI RFFE bus is is 2-wire serial i...

896 1.0

MIPI RFFE Slave Controller IP Core Mobile radio communication is trending towards complex multi-radio systems comprising of several transceivers. The MIPI RFFE bus is is 2-wire serial i...

897 1.0

MIPI LLI Controller - (Low Latency Interface) The Low Latency interface (LLI) is a point-to point-interconnect that allows two devices on the separate chips to communicate as if a device attached ...

898 50.0

MIPI D-PHY Universal Tx / Rx v1.1 @1.5ghz Ultra Low Power for IoT & Wearables Arasan 2nd Generation MIPI D-PHY v1.1 IP supporting speeds of up to 1.5 Gbps on TSMC 22nm process technology for SoC designs. Arasan’s D-PHY IP is ava...

899 60.0

MIPI I3C PHY - TSMC (12nm, 7nm, 5nm, and 22nm) - GF 12nm The I3C bus (incl. PHY) is used for various sensors in the mobile/automotive system where the Host transfers data and control between itself and vario...

900 0.0

UFS 3.1 Host Controller compatible with M-PHY 4.1 and UniPro 1.8 The Arasan UFS Host -UniPro IP is a simple, high performance, serial interface used primarily in mobile systems between host processing and NVM mass s...