901 0.0

MIPI D-PHY CSI-2 TX (Transmitter) in GlobalFoundries 22FDX The MXL-DPHY-CSI-2-TX-GF-22FDX is a high-frequency low-power, low-cost, source synchronous, Physical Layer supporting the MIPI Alliance Specification ...

902 10.0

Interlaken Controller Interlaken is a scalable chip-to-chip protocol, which ensures the integrity of reliable data transfer and managing data flows to prevent data overload...

903 10.0

MIPI I3C Controller and Target fully featured IP solution The MIPI I3C Controller IP is a highly optimized and technology-agnostic implementation of the MIPI I3C v.1.1.1 standard targeting both ASIC and F...

904 20.0

Camera SLVS-EC 2.0 Receiver 5.0Gbps 8-Lane * The CL12812M8RIP5000 is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to ISP (Imaging Signal Processor) and DSP. The CL12812M8RI...

905 0.0

MIPI D-PHY 4 Lane CSI-2 TX (Transmitter) in TowerJazz 110nm The MXL-DPHY-CSI-2-TX is a high-frequency low-power, low-cost, source synchronous, Physical Layer supporting the MIPI Alliance Standard for D-PHY. The...

906 40.0

Camera SLVS-EC 3.0 Receiver 10.0Gbps 8-Lane * The CL12812M8RIP10000 is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to ISP (Imaging Signal Processor) and DSP. The CL12812M...

907 15.0

Camera SLVS-EC 3.0 Transmitter 10.0Gbps 8-Lane * The CL12811M8TIP10000 TXPHY supports 8 TX DATA lanes for up to 10Gbps application. A wide range phase-locked clock is embedded in the IP to suppor...

908 0.0

Display LVDS single link/dual link Transmitter 1.12Gbps 8-Lane * The CL12491M8TIP160 transmitter converts parallel RGB data and 4bits of HYNC,VSYNC,DE and Control) of CMOS parallel data into serial LVDS data strea...

909 7.0

Display Controller - LCD / OLED Panels (AHB Bus) The Digital Blocks DB9000AHB TFT LCD Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA 2.0 AHB Bus to a TFT LCD pane...

910 3.0

I2C Master Controller w/FIFO (APB Bus) The Digital Blocks DB-I2C-M-APB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC, or other high performance microprocessor via the AMBA 2.0 AP...

911 0.0

RGB to CCIR 601 / 656 Encoder The Digital Blocks DB1892AXI RGB to CCIR 601 / CCIR 656 Encoder interfaces RGB data along with synchronization signals from a LCD Controller such as D...

912 1.0

BitBLT Graphics Hardware Accelerator (AXI Bus) The Digital Blocks DB9100AXI3 BitBLT Graphics Hardware Accelerator Verilog IP Core renders a graphics frame by generating new bitmaps from commands to...

913 1.0

BitBLT Graphics Hardware Accelerator (AHB Bus) The Digital Blocks DB9100AHB BitBLT Graphics Hardware Accelerator Verilog IP Core renders a graphics frame by generating new bitmaps from commands to ...

914 0.0

BitBLT Graphics Hardware Accelerator (AXI4 Bus) The Digital Blocks DB9100AXI4 BitBLT Graphics Hardware Accelerator Verilog IP Core renders a graphics frame by generating new bitmaps from commands to...

915 1.0

I2C Master / Slave Controller w/FIFO (AXI & AXI-Lite Bus) The Digital Blocks DB-I2C-MS-AXI Controller IP Core interfaces a microprocessor via the AXI system Interconnect Fabric to an I2C Bus. The I2C is a t...

916 0.0

MIPI D-PHY DSI TX+ (Transmitter) IP in Samsung 28FDSOI The MXL-DPHY-DSI-TX+ is a high-frequency low-power, source-synchronous, physical layer supporting the MIPI Alliance Specification for D-PHY v2.1, whic...

917 3.0

I2C Master / Slave Controller w/FIFO (AHB & AHB-Lite Bus) The Digital Blocks DB-I2C-MS-AHB Controller IP Core interfaces a microprocessor via the AHB system Interconnect Fabric to an I2C Bus. The I2C is a t...

918 3.0

I2C Master / Slave Controller w/FIFO (APB Bus) The Digital Blocks DB-I2C-MS-APB Controller IP Core interfaces a microprocessor via the APB system Interconnect Fabric to an I2C Bus. The I2C is a t...

919 0.0

I2C Master Controller w/FIFO (AHB & AHB-Lite Bus) The Digital Blocks DB-I2C-M-AHB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC, or other high performance microprocessor via the AMBA 2.0 AP...

920 0.0

I2C Master Controller w/FIFO (AXI & AXI-Lite Bus) The Digital Blocks DB-I2C-M-AXI Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC, or other high performance microprocessor via the AMBA 2.0 AX...

921 11.0

DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Command Stream List The Digital Blocks DB-DMAC-MC2-CS-MM2S-S2MM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Memo...

922 0.0

eSPI & SPI Master Controller w/FIFO The Digital Blocks DB-eSPI-SPI-M-AMBA is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting the addition of Enhanced SPI (eSPI)...

923 0.0

eSPI & SPI Slave Controller w/FIFO The Digital Blocks DB-eSPI-SPI-S-AMBA is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting the addition of Enhanced SPI (eSPI)...

924 1.0

RTP / UDP / IP Hardware Stack for H.264/H.265 NAL Video Streams Packet Processing The Digital Blocks DB-RTP-UDP-IP-NAL IP Core is a RTP/UDP/IP Protocol Hardware Stack with MAC Layer Pre- & Post-Processors and an ARP Packet Processor...

925 0.0

I2CM - DI2CM - I2C Bus Interface - Master The I2C is a two-wire, bi-directional serial bus, that provides a simple and efficient method of short distance data transmission between many devices...

926 0.0

I2CS - DI2CS - Slave I2C bus controller with FIFO The DI2CS core provides an interface between a microprocessor / microcontroller and I2C bus. It can work as: - a slave transmitter or - slave rece...

927 0.0

MIPI D-PHY CSI-2 TX (Transmitter) in TSMC 65nm The MXL-DPHY-CSI-2-TX is a high-frequency low-power, low-cost, source synchronous, Physical Layer supporting the MIPI Alliance Specification for D-PHY...

928 0.0

I2CSB - DI2CSB - I2C Bus Interface Slave -Base version The I2C is a two-wire, bi-directional serial bus, which provides a simple and efficient method of short distance data transmission between many device...

929 0.0

I2CMS - DI2CMS - I2C Bus Interface - Master/Slave The DI2CMS is a flexible and robust interface solution that bridges microprocessors with an I2C (Inter-Integrated Circuit) bus, offering support for b...

930 0.0

USB2 - DUSB2 - USB 2.0 Device Controller The DUSB2 is hardware implementation of full/high-speed peripheral controller that interfaces to the UTMI bus transceiver. The DUSB2 contains the USB ...

931 5.0

I3C - DI3CM-HCI - MIPI I3C Basic v1.1.1 specifications with Host Controller Interface v1.1 specification The I3C (Improved Inter-Integrated Circuit) is the successor of the I2C bus. Keeping the best assets from its elder brother, the I3C has major improve...

932 0.3729

PCI/PCIX Interface 2.5V Device - TSMC 28nm 28HP (CLN28HP) Dolphin's interface IP for standard I/O and specialty I/O delivers ultra high performance for DDR1/2/3/4, LPDDR2/3, DDR PHY, LVDS, LVPECL, I2C, PCI, S...

933 0.3729

PCI/PCIX Interface 2.5V Device - TSMC 40nm 40G (CLN40G) Dolphin's hardened DDR2/3/4 SDRAM PHY and LPDDR2/3 SDRAM PHY IP is a silicon-proven, Combo PHY supporting speeds up to 2133 Mbps. It is fully complian...

934 0.3729

PCI/PCIX Interface 2.5V Device - TSMC 40nm 40LP (CLN40lp) Dolphin's hardened DDR2/3/4 SDRAM PHY and LPDDR2/3 SDRAM PHY IP is a silicon-proven, Combo PHY supporting speeds up to 2133 Mbps. It is fully complian...

935 1.0

Digital Down Converter core The eSi-DDC is a Digital Down Converter combining a Digital Frequency Synthesizer (DDS) with a Digital Mixer. The DDS is implemented in a resource ef...

936 0.0

MIPI C-PHY CSI-2 TX+ (Transmitter) IP in TSMC 40ULP The MXL-CPHY-2p5G-CSI-2-TX+-T-40ULP is a high-frequency low-power, low-cost, source-synchronous, physical Layer. The PHY is configured as a MIPI Maste...

937 0.0

Digital IIR filter with APB interface A range of 5th to 11th order digital IIR filters for conditioning and optionally decimating data from an external source and to DMA the output into pr...

938 0.0

APB peripheral implementing the functionality of the ETSI TS 102613 V7.9.0 (2011-03) MAC Layer The eSi-SWP MAC is an APB peripheral and implements the functionality of the ETSI TS 102 613 V7.9.0 (2011-03) MAC Layer....

939 0.118

APB Fundamental Peripheral IP, Serial Interface controller for multiple frame formats, SSP (by TI), SPI (by Motorola), Microwire (by NS), I2S (by Philips), AC - link (by Intel) and SPDIF (by Intel), Soft IP Synchronous serial port interface controller with APB interface....

940 0.118

Direct memory access controller with AHB interface Direct memory access controller with AHB interface....

941 0.118

APB Fundamental Peripheral IP, I2C controller, Soft IP I2C bus interface controller with APB interface....

942 0.118

USB 1.1 Device Controller IP, Soft IP USB 1.1 device controller with AHB interface....

943 0.118

USB 2.0 Device Controller IP, Device controller, Soft IP USB 2.0 device controller....

944 0.118

USB 1.1.OTG PHY IP, OTG, UMC 0.18um G2 process USB 1.1 On-The-Go transceiver (ECN spec), UMC 0.18um GII Logic process....

945 0.118

AHB system Peripheral IP, IDE Host controller, Soft IP IDE host controller with AHB interface....

946 0.118

APB Fundamental Peripheral IP, IO controller, Soft IP General purpose input/output controller with APB interface....

947 0.0

MIPI D-PHY Universal IP - 4.5Gbps/lane, MIPI D-PHY v2.5 Compliant in TSMC 22ULP The MXL-DPHY-v2.5-UNIV-T-22ULP is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification...

948 0.118

APB Fundamental Peripheral IP, Keyboard/Mouse controller, Configurable keypad matrix from 4x4 to 8x16, Soft IP Keyboard/Mouse controller with APB interface....

949 0.118

AHB system Peripheral IP, SDRAM controller, Soft IP Synchronous DRAM controller with AHB interface....

950 0.118

AHB system Peripheral IP, SRAM controller, Soft IP Static memory controller with AHB interface....