951 0.0

PCI Master/Target Interface Core ...

952 0.0

32-bit, 33 MHz Multifunction Target Interface The PCI-T32MF implements a target-only PCI interface compliant with the PCI 2.3 specification. It supports a 32-bit address/data bus and operates up t...

953 0.0

32-bit/33,66Mhz PCI Host Bridge ...

954 0.0

AMBA AHB to APB Bus Bridge Core The AHB2APB implements an AHB to APB bus bridge, allowing the connection of peripherals with an APB interface to an AHB bus. The highly-configurable...

955 0.0

General-Purpose I/O Controller Core The GPIO core is used to create functions in a system that are not implemented with dedicated controllers, and require simple input and/or output soft...

956 0.0

Internal Synchronous SRAM Controller Core The SRAM-CTRL implements a SRAM Controller providing a standard AHB/APB interface to translate AHB/APB bus reads and writes into reads and writes with...

957 0.0

Multi-Function PCI Master/Target Interface Core The PCI-M32MF implements a master/target PCI interface compliant with the PCI 2.3 specification. It supports a 32-bit address/data bus and operates up...

958 5.0

MIPI I3C Basic Target The I3C-T core implements a versatile MIPI® Improved Inter Integrated Circuit (I3C) Target controller core suitable for any I3C bus topology & complia...

959 100.0

MIPI D-PHY Universal IP in TSMC 22ULP The MXL-DPHY-UNIV is a high-frequency low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for D-PHY v2....

960 10.0

I2C and SPI Master/Slave Controller The I2CSPI-CTRL is a compact and versatile serial interface controller supporting both SPI (Serial Peripheral Interface) and I2C (Inter-Integrated Cir...

961 25.0

MIPI D-PHY CSI-2 TX (Transmitter) in GlobalFoundries 22FDX The MXL-DPHY-CSI-2-TX is a high-frequency low-power, low-cost, source synchronous, Physical Layer supporting the MIPI Alliance Specification for D-...

962 15.0

Interlaken Controller Interlaken is a scalable chip-to-chip protocol, which ensures the integrity of reliable data transfer and managing data flows to prevent data overload...

963 15.0

MIPI I3C Controller and Target fully featured IP solution The MIPI I3C Controller IP is a highly optimized and technology-agnostic implementation of the MIPI I3C v.1.1.1 standard targeting both ASIC and F...

964 30.0

Universal Chiplet Interconnect Express (UCIe) Controller Integrating multiple chiplets within a single package has become crucial for high-performance computing. CoMira’s UCIe (Universal Chiplet Interconnect...

965 20.0

Camera SLVS-EC 2.0 Receiver 5.0Gbps 8-Lane * The CL12812M8RIP5000 is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to ISP (Imaging Signal Processor) and DSP. The CL12812M8RI...

966 0.0

MIPI D-PHY 4 Lane CSI-2 TX (Transmitter) in TowerJazz 110nm The MXL-DPHY-CSI-2-TX is a high-frequency low-power, low-cost, source synchronous, Physical Layer supporting the MIPI Alliance Standard for D-PHY. The...

967 40.0

Camera SLVS-EC 3.0 Receiver 10.0Gbps 8-Lane * The CL12812M8RIP10000 is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to ISP (Imaging Signal Processor) and DSP. The CL12812M...

968 15.0

Camera SLVS-EC 3.0 Transmitter 10.0Gbps 8-Lane * The CL12811M8TIP10000 TXPHY supports 8 TX DATA lanes for up to 10Gbps application. A wide range phase-locked clock is embedded in the IP to suppor...

969 0.0

Display LVDS single link/dual link Transmitter 1.12Gbps 8-Lane * The CL12491M8TIP160 transmitter converts parallel RGB data and 4bits of HYNC,VSYNC,DE and Control) of CMOS parallel data into serial LVDS data strea...

970 7.0

Display Controller - LCD / OLED Panels (AHB Bus) The Digital Blocks DB9000AHB TFT LCD Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA 2.0 AHB Bus to a TFT LCD pane...

971 3.0

I2C Master Controller w/FIFO (APB Bus) The Digital Blocks DB-I2C-M-APB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC, or other high performance microprocessor via the AMBA 2.0 AP...

972 0.0

RGB to CCIR 601 / 656 Encoder The Digital Blocks DB1892AXI RGB to CCIR 601 / CCIR 656 Encoder interfaces RGB data along with synchronization signals from a LCD Controller such as D...

973 1.0

BitBLT Graphics Hardware Accelerator (AXI Bus) The Digital Blocks DB9100AXI3 BitBLT Graphics Hardware Accelerator Verilog IP Core renders a graphics frame by generating new bitmaps from commands to...

974 1.0

BitBLT Graphics Hardware Accelerator (AHB Bus) The Digital Blocks DB9100AHB BitBLT Graphics Hardware Accelerator Verilog IP Core renders a graphics frame by generating new bitmaps from commands to ...

975 0.0

BitBLT Graphics Hardware Accelerator (AXI4 Bus) The Digital Blocks DB9100AXI4 BitBLT Graphics Hardware Accelerator Verilog IP Core renders a graphics frame by generating new bitmaps from commands to...

976 1.0

I2C Master / Slave Controller w/FIFO (AXI & AXI-Lite Bus) The Digital Blocks DB-I2C-MS-AXI Controller IP Core interfaces a microprocessor via the AXI system Interconnect Fabric to an I2C Bus. The I2C is a t...

977 1.0

MIPI D-PHY DSI TX+ (Transmitter) IP in Samsung 28FDSOI The MXL-DPHY-DSI-TX+ is a high-frequency low-power, source-synchronous, physical layer supporting the MIPI Alliance Specification for D-PHY v2.1, whic...

978 3.0

I2C Master / Slave Controller w/FIFO (AHB & AHB-Lite Bus) The Digital Blocks DB-I2C-MS-AHB Controller IP Core interfaces a microprocessor via the AHB system Interconnect Fabric to an I2C Bus. The I2C is a t...

979 3.0

I2C Master / Slave Controller w/FIFO (APB Bus) The Digital Blocks DB-I2C-MS-APB Controller IP Core interfaces a microprocessor via the APB system Interconnect Fabric to an I2C Bus. The I2C is a t...

980 0.0

I2C Master Controller w/FIFO (AHB & AHB-Lite Bus) The Digital Blocks DB-I2C-M-AHB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC, or other high performance microprocessor via the AMBA 2.0 AP...

981 0.0

I2C Master Controller w/FIFO (AXI & AXI-Lite Bus) The Digital Blocks DB-I2C-M-AXI Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC, or other high performance microprocessor via the AMBA 2.0 AX...

982 11.0

DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Command Stream List The Digital Blocks DB-DMAC-MC2-CS-MM2S-S2MM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Memo...

983 0.0

eSPI & SPI Master Controller w/FIFO The Digital Blocks DB-eSPI-SPI-M-AMBA is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting the addition of Enhanced SPI (eSPI)...

984 0.0

eSPI & SPI Slave Controller w/FIFO The Digital Blocks DB-eSPI-SPI-S-AMBA is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting the addition of Enhanced SPI (eSPI)...

985 1.0

RTP / UDP / IP Hardware Stack for H.264/H.265 NAL Video Streams Packet Processing The Digital Blocks DB-RTP-UDP-IP-NAL IP Core is a RTP/UDP/IP Protocol Hardware Stack with MAC Layer Pre- & Post-Processors and an ARP Packet Processor...

986 0.0

I2CM - DI2CM - I2C Bus Interface - Master The I2C is a two-wire, bi-directional serial bus, that provides a simple and efficient method of short distance data transmission between many devices...

987 0.0

I2CS - DI2CS - Slave I2C bus controller with FIFO The DI2CS core provides an interface between a microprocessor / microcontroller and I2C bus. It can work as: - a slave transmitter or - slave rece...

988 0.0

MIPI D-PHY CSI-2 TX (Transmitter) in TSMC 65nm The MXL-DPHY-CSI-2-TX is a high-frequency low-power, low-cost, source synchronous, Physical Layer supporting the MIPI Alliance Specification for D-PHY...

989 0.0

I2CSB - DI2CSB - I2C Bus Interface Slave -Base version The I2C is a two-wire, bi-directional serial bus, which provides a simple and efficient method of short distance data transmission between many device...

990 0.0

I2CMS - DI2CMS - I2C Bus Interface - Master/Slave The DI2CMS is a flexible and robust interface solution that bridges microprocessors with an I2C (Inter-Integrated Circuit) bus, offering support for b...

991 0.0

USB2 - DUSB2 - USB 2.0 Device Controller The DUSB2 is hardware implementation of full/high-speed peripheral controller that interfaces to the UTMI bus transceiver. The DUSB2 contains the USB ...

992 5.0

I3C - DI3CM-HCI - MIPI I3C Basic v1.1.1 specifications with Host Controller Interface v1.1 specification The I3C (Improved Inter-Integrated Circuit) is the successor of the I2C bus. Keeping the best assets from its elder brother, the I3C has major improve...

993 0.3729

PCI/PCIX Interface 2.5V Device - TSMC 28nm 28HP (CLN28HP) Dolphin's interface IP for standard I/O and specialty I/O delivers ultra high performance for DDR1/2/3/4, LPDDR2/3, DDR PHY, LVDS, LVPECL, I2C, PCI, S...

994 0.3729

PCI/PCIX Interface 2.5V Device - TSMC 40nm 40G (CLN40G) Dolphin's hardened DDR2/3/4 SDRAM PHY and LPDDR2/3 SDRAM PHY IP is a silicon-proven, Combo PHY supporting speeds up to 2133 Mbps. It is fully complian...

995 0.3729

PCI/PCIX Interface 2.5V Device - TSMC 40nm 40LP (CLN40lp) Dolphin's hardened DDR2/3/4 SDRAM PHY and LPDDR2/3 SDRAM PHY IP is a silicon-proven, Combo PHY supporting speeds up to 2133 Mbps. It is fully complian...

996 3.0

Configurable AES Core eSi-AES is a range of sophisticated AES cores for use in ASIC or FPGA technologies. They can be configured to customer the requirements to enable a...

997 1.0

Digital Down Converter core The eSi-DDC is a Digital Down Converter combining a Digital Frequency Synthesizer (DDS) with a Digital Mixer. The DDS is implemented in a resource ef...

998 1.0

RSA public key cryptography with APB interface The standard RSA module is available as an APB peripheral, where it seamlessly integrates with EnSilica's cryptography library. The peripheral can be...

999 10.0

MIPI C-PHY CSI-2 TX+ (Transmitter) IP in TSMC 40ULP The MXL-CPHY-CSI-2-TX+ is a high-frequency low-power, low-cost, source-synchronous, physical Layer. The PHY is configured as a MIPI Master supporting ...

1000 0.0

Digital IIR filter with APB interface A range of 5th to 11th order digital IIR filters for conditioning and optionally decimating data from an external source and to DMA the output into pr...