1101 1.0

DP/eDP1.4/1.2 RX PHY Innosilicon DP RX PHY is designed to receive and recover the video, audio and auxiliary data from a DP or eDP source device for display applications. ...

1102 0.0

DP1.4 TX PHY Innosilicon eDP TX PHY is designed to transmit video, audio, and auxiliary data from a system host device to a display device for display applications...

1103 1.0

DP/eDP1.4/1.2 TX PHY&controller Innosilicon eDP TX PHY is designed to transmit video, audio, and auxiliary data from a system host device to a display device for display applications...

1104 0.0

eDP1.4 Transmitter PHY Innosilicon eDP TX IP is designed to transmit video, audio and auxiliary data from system host device to a display device for display applications. I...

1105 1.0

HDMI1.4 Receiver PHY Innosilicon HDMI RX IP is designed to receive and recover the video and audio data from an HDMI source device for display applications. Innosilicon H...

1106 1.0

HDMI1.4 Transmitter IP Innosilicon HDMI TX IP is designed for transmitting video and audio data from a video source device to a display device, which is compatible with HDMI...

1107 1.0

HDMI2.0/1.4 RX PHY & Controller Innosilicon HDMI RX IP is designed to receive and recover the video and audio data from a HDMI source device for display applications, which is compat...

1108 1.0

HDMI2.0 Receiver PHY Innosilicon HDMI RX IP is designed to receive and recover the video and audio data from an HDMI source device for display applications. Innosilicon H...

1109 102.0

MIPI C-PHY/D-PHY Combo DSI TX+ IP 4.5Gsps/4.5Gbps in TSMC N5 The MXL-CDPHY-4p5G-DSI-TX+-T-5N is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specificatio...

1110 1.0

HDMI2.0 Receiver PHY & Controller Innosilicon HDMI RX IP is composed of the digital controller, the PHY logic and physical layer. The digital controller receives video, audio, synchron...

1111 1.0

HDMI2.0 TX Controller Innosilicon HDMI TX Controller is designed for transmitting video and audio data from a video source device to a display device, which is compatible w...

1112 1.0

HDMI2.0/1.4 TX PHY & Controller Innosilicon HDMI TX IP is designed for transmitting video and audio data from a video source device to a display device, which is compatible with HDMI...

1113 1.0

HDMI2.0 TX PHY Innosilicon HDMI TX IP is designed for transmitting video and audio data from a video source device to a display device, which is compatible with HDMI...

1114 1.0

HDMI2.1 TX Controller Innosilicon HDMI TX Controller is designed for transmitting video and audio data from a video source device to a display device, which is compatible w...

1115 1.0

HDMI2.1 TX PHY Innosilicon HDMI TX PHY IP is designed for transmitting video and audio data from a video source device to a display device, which is compatible with ...

1116 1.0

HDMI2.1 Transmitter PHY & Controller Innosilicon HDMI TX IP is designed for transmitting video and audio data from a video source device to a display device, which is compatible with HDMI...

1117 4.0

SAS Initiator Core The IntelliProp IPC-SS105A-HI SAS Initiator Core is an industry standard Serial-SCSI (SAS) initiator core that enables host designs to connect to high...

1118 4.0

SAS Target Core The IntelliProp IPC-SS107A-DT SAS Target Core is an industry standard Serial-SCSI (SAS) Core that enables device applications to connect to high throu...

1119 4.0

SATA "Y" RAID Bridge without NCQ The IntelliProp IPP-SA112A-BR SATA “Y” Bridge with RAID design provides SATA compliant connections and a standard SATA interface that performs RAID0 t...

1120 11.0

MIPI D-PHY IP 4.5Gbps in TSMC N7 The MXL-DPHY-DSI-TX-T-N07 is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for ...

1121 4.0

SATA Host App Core IntelliProp’s SATA host core (IPC-SA101A-HI) is an industry standard Serial-ATA (SATA) host interface core that enables host application companies to ...

1122 4.0

SATA RAID Core The IntelliProp IPC-BL109A-RD SATA RAID Core is a hardware design block written in HDL that performs RAID 0 operations to provide higher performance a...

1123 4.0

SATA "Y" Bridge The IntelliProp SATA "Y" Bridge design (IPP-SA111A-BR) provides SATA compliant connections per SATA-IO 3.3 and a standard SATA interface to access dri...

1124 4.0

SATA Device ADCI Core IntelliProp’s SATA Device ADCI core (IPC-SA155A-DT) is an industry standard Serial-ATA (SATA) device interface core that allows companies to build hig...

1125 4.0

SATA 1-to-1 Speed Bridge with Sandbox The IntelliProp SATA 1-to-1 Speed Bridge with Sandbox (IPP-SA110A-BR) design provides SATA compliant connections to a SATA host and a SATA device. The...

1126 1.0

25G Multi-SerDes PHY The Innosilicon 25G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 25Gbps within a single lane. For this particular datash...

1127 1.0

12.5G Multi-SerDes PHY The Innosilicon 12.5G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 12.5Gbps within a single lane. For this particular da...

1128 1.0

10G Multi-SerDes PHY The Innosilicon 10G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 10Gbps within a single lane. The PHY can be configured ...

1129 1.0

32G Multi-SerDes For PCIe5.0/USB3.x PHY The Innosilicon 32G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 32Gbps within a single lane. For this datasheet, the PH...

1130 0.0

Mil-Std-1553B/AS15531 Interface The GR1553B core implements the MIL-STD-1553B (Notice 2) data bus protocol, with ability to serve as Bus Controller (BC), Remote Terminal (RT) or Bus ...

1131 0.0

MIPI C-PHY/D-PHY Combo CSI-2 TX+ IP 3.5Gsps/2.5Gbps, 2T/2L The MXL-CDPHY-CSI-2-TX+-40LP is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification f...

1132 0.0

Highly configurable high-speed serial link controller The GRHSSL IP is a highly configurable high-speed serial link controller, described in VHDL. It can implement: * SpaceFibre controller (GRSPFI) * W...

1133 0.0

V-By-One Receiver_8ch Innosilicon VBO RX IP is designed to receive and recover the video data from a VBO source device for display applications. Innosilicon VBO RX IP is c...

1134 0.0

Video-by-One Receiver IP_16ch This document introduces the low power Innosilicon Video-by-One (VBO) Receiver IP containing PHY and controller. Innosilicon VBO RX is designed for re...

1135 0.0

Video-by-One Transmitter IP_8ch Innosilicon VBO TX IP is designed for transmitting video data from a video source device to a display device. It is compatible with V-By-One HS 1.4 st...

1136 0.0

V-By-One PHY & Controller (Tx+ Rx) INNOSILICON™ VBO IP is designed for transmitting or receiving video signals between a video source device and display device, The IP is fully complian...

1137 1.0

I2C MAster Slave The MI2CMS macro implements a synchronous single-chip I2C Master and Slave Macro capable of linking one CPU to one I2C-bus. Communication with I2C-bus...

1138 1.0

I2C Master The MI2CM macro implements a synchronous single-chip I2C Master only Macro capable of linking one CPU to one I2C-bus. Communication with I2C-bus is ca...

1139 0.0

AHB Low Power Subsystem - ARM Cortex M0 The AHB Low Power Subsystem is an AMBA® based system that is useful as the basic digital infrastructure for building low power SOCs. The subsystem co...

1140 1.0

I2C Slave The MI2CS macro implements a synchronous single-chip I2C Slave Macro capable of linking one CPU to one I2C-bus. Communication with I2C-bus is carried ...

1141 1.0

SATA HOST Synchronous IP The LDS SATA HOST XV5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA. The LDS SATA HOST XV5 IP is com...

1142 1.0

Serial ATA Dual Host Controller The LDS_SATA HOST DUAL XV5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA. The LDS SATA HOST DUAL XV5...

1143 1.0

SATA Host controller on Virtex 5 FXT The LDS SATA HOST XF5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA. The LDS SATA HOST XV5 IP is com...

1144 1.0

Dual SATA Host controller on Virtex 5 FXT FPGA The LDS SATA HOST DUAL XF5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA. The LDS SATA HOST DUAL XF5...

1145 1.0

SATA Host Controller The LDS SATA HOST STR4GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA Startix IV GX FPGA. Th...

1146 1.0

SATA Host Controller on Spartan 6 LXT FPGA The LDS SATA HOST SP6 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Spartan 6 FPGA. The LDS SATA HOST SP6 IP is co...

1147 1.0

SATA Host Controller on Virtex 6 LXT The LDS SATA HOST XV6 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 6 FPGA. The LDS SATA HOST XV6 IP is com...

1148 1.0

SATA III HOST Controller on Virtex 6 The LDS SATA 3 HOST XV6 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 6 speed grade 2 FPGA. The LDS SATA 3 ...

1149 1.0

SATA Host on Altera Arria II GX The LDS SATA HOST AR2GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA ARRIA II GX FPGA. The L...

1150 0.0

AHB Performance Subsystem - ARM Cortex M3 The AHB Performance Subsystem is an AMBA® based system that is useful as the digital infrastructure for building low power SOCs needing additional per...